1、七、綜合題：（20分）（一）已知狀態(tài)機(jī)狀態(tài)圖如圖a所示；完成下列各題：圖a 狀態(tài)圖圖b 狀態(tài)機(jī)結(jié)構(gòu)圖1. 試判斷該狀態(tài)機(jī)類型，并說(shuō)明理由。該狀態(tài)機(jī)為moore型狀態(tài)機(jī)，輸出數(shù)據(jù)outa和輸入ina沒(méi)有直接邏輯關(guān)系，outa是時(shí)鐘clk的同步時(shí)序邏輯。2. 根據(jù)狀態(tài)圖，寫(xiě)出對(duì)應(yīng)于結(jié)構(gòu)圖b，分別由主控組合進(jìn)程和主控時(shí)序進(jìn)程組成的VHDL有限狀態(tài)機(jī)描述。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MOOREB ISPORT (CLK, RESET : IN STD_LOGIC; INA : IN STD_LOGIC_VECTOR (1 DOWNTO

2、 0);OUTA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END MOOREB;ARCHITECTURE ONE OF MOOREB ISTYPE MS_STATE IS (ST0, ST1, ST2, ST3);SIGNAL C_ST, N_ST : MS_STATE;BEGINPROCESS (CLK, RESET)BEGINIF RESET = 1 THEN C_ST = ST0;ELSIF CLKEVENT AND CLK = 1 THEN C_ST IF INA = “00” THEN N_ST = ST0; ELSE N_ST = ST1;END

3、 IF;OUTA IF INA = “00” THEN N_ST = ST1;ELSE N_ST = ST2;END IF;OUTA IF INA = “11” THEN N_ST = ST0;ELSE N_ST = ST3;END IF;OUTA IF INA = “11” THEN N_ST = ST3;ELSE N_ST = ST0;END IF;OUTA N_ST = ST0;END CASE;END PROCESS;END ONE;3. 若已知輸入信號(hào)如下圖所示，分析狀態(tài)機(jī)的工作時(shí)序，畫(huà)出該狀態(tài)機(jī)的狀態(tài)轉(zhuǎn)換值（c_state）和輸出控制信號(hào)(out_a)；4. 若狀態(tài)機(jī)仿真過(guò)程中出現(xiàn)

4、毛刺現(xiàn)象，應(yīng)如何消除；試指出兩種方法，并簡(jiǎn)單說(shuō)明其原理。方法1，添加輔助進(jìn)程對(duì)輸出數(shù)據(jù)進(jìn)行鎖存方法2，將雙進(jìn)程狀態(tài)機(jī)改寫(xiě)為單進(jìn)程狀態(tài)機(jī)，其輸出也是鎖存過(guò)了，故能消除毛刺方法3，使用狀態(tài)位直接輸出型狀態(tài)機(jī)編碼方式，其輸出直接由當(dāng)前狀態(tài)輸出，也沒(méi)有毛刺七、綜合題：（20分）根據(jù)如下所示狀態(tài)圖及其狀態(tài)機(jī)結(jié)構(gòu)圖，回答問(wèn)題1.試判斷該狀態(tài)機(jī)類型，并說(shuō)明理由。改狀態(tài)機(jī)可以為mealy型狀態(tài)機(jī)，當(dāng)輸入ina變化時(shí)可影響輸出outa立即變化2.請(qǐng)問(wèn)如何消除狀態(tài)機(jī)輸出信號(hào)毛刺？試列出至少兩種方法，并說(shuō)明理由。方法1，添加輔助進(jìn)程對(duì)輸出數(shù)據(jù)進(jìn)行鎖存方法2，將雙進(jìn)程狀態(tài)機(jī)改寫(xiě)為單進(jìn)程狀態(tài)機(jī)，其輸出也是鎖存過(guò)了，故能

5、消除毛刺方法3，使用狀態(tài)位直接輸出型狀態(tài)機(jī)編碼方式，其輸出直接由當(dāng)前狀態(tài)輸出，也沒(méi)有毛刺3.試由b、c兩圖中任選一圖寫(xiě)出其完整的VHDL程序。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY EX7 ISPORT (CLK, RESET: IN STD_LOGIC;INA: IN STD_LOGIC_VECTOR(2 DOWNTO 0);OUTA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END EX7;- MOORE型狀態(tài)機(jī)ARCHITECTURE ONE OF EX7 ISTYPE STATE IS (S0, S1

6、, S2, S3);SIGNAL C_ST : STATE;BEGINPROCESS (CLK, RESET, INA)BEGINIF RESET = 1 THEN C_ST = S0; OUTA 0);ELSIF RISING_EDGE(CLK) THENCASE C_ST ISWHEN S0 =IF INA = 101 THEN OUTA = 0010;ELSIF INA = 111 THEN OUTA = 1100;END IF;C_ST IF INA = 000 THEN C_ST = S1;ELSIF INA = 110 THEN C_ST = S2;END IF;OUTA IF I

7、NA = 100 THEN C_ST = S2;ELSIF INA = 011 THEN C_ST = S1;ELSE C_ST = S3;END IF;OUTA IF INA = 101 THEN OUTA = 1101;ELSIF INA = 011 THEN OUTA = 1110;END IF;C_ST C_ST = S0;OUTA 0);END CASE;END IF;END PROCESS;END ONE;- MEALY型狀態(tài)機(jī)ARCHITECTURE TWO OF EX7 ISTYPE STATE IS (S0, S1, S2, S3);SIGNAL C_ST, N_ST : S

8、TATE;BEGINREG : PROCESS (CLK, RESET)BEGINIF RESET = 1 THEN C_ST = S0;ELSIF CLKEVENT AND CLK = 1 THENC_ST N_ST = S1;IF INA = 101 THEN OUTA = 0010;ELSIF INA = 111 THEN OUTA = 1100;ELSE OUTA OUTA = 1001;IF INA = 000 THEN N_ST = S1;ELSIF INA = 110 THEN N_ST = S2;ELSE N_ST OUTA = 1111;IF INA = 100 THEN N

9、_ST = S2;ELSIF INA = 011 THEN N_ST = S1;ELSE N_ST IF INA = 101 THEN OUTA = 1101;ELSIF INA = 011 THEN OUTA = 1110;ELSE OUTA = 0000;END IF;N_ST N_ST = S0;OUTA 0);END CASE;END PROCESS;END TWO;（二） 已知一個(gè)簡(jiǎn)單的波形發(fā)生器的數(shù)字部分系統(tǒng)框圖如下圖所示圖中l(wèi)cnt、lrom都是在MAX+PlusII中使用MegaWizard調(diào)用的LPM模塊，其VHDL描述中Entity部分分別如下：ENTITY lcnt IS

10、PORT(clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END lcnt;ENTITY lrom ISPORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END lrom;試用VHDL描述該系統(tǒng)的頂層設(shè)計(jì)（使用例化語(yǔ)句）。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MYSG ISPORT (CLK : IN STD_LOGIC;TO_DA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) );END MYSQ;ARCHITECTURE ONE OF MYSQ ISSIGNAL ADDR : STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT LCNTPORT (CLOCK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) );END COMPONENT;COMPONENT LROMPORT (ADDRESS : IN STD_LOGIC_VECTOR