1、Technical English,For Information Science and Electronic Engineering,Unit 2,Integrated Circuits,Part I,The Integrated Circuit,3,New Words,4,New Words,5,1,Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can

2、be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.1,由稱為晶體管的電子開關得到它們的（各種）功能,粗略地說，晶體管好似一種電子控制閥，由此加在閥一端的能量可以使能量在另外兩個連接端之間流動。,6,1,By combining multiple transistors, digital logic building blocks suc

3、h as AND gates and flip-flops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.2,查閱大學化學書中的元素周期表，你會查到半導體是介于金屬與非金屬之間的一類元素。,

4、7,1,They are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differing electrical properties can be accurately controlled by mixing the semiconductor with s

5、mall amounts of other elements.,可使半導體像金屬那樣導電，或者像非金屬那樣絕緣。,8,1,This mixing is called doping. A semiconductor can be doped to contain more electrons (N-type) or fewer electrons (P-type). Examples of commonly used semiconductors are silicon and germanium. Phosphorous and boron are two elements that are

6、used to dope N-type and P-type silicon, respectively.3,N型硅半導體摻入磷元素，而P型硅半導體摻入硼元素。,9,2,A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common types of transistors, the bipolar-junction transistor (BJT) and the field-effect transistor (FET) are

7、 schematically illustrated in Figure 2.1.,圖2.1給出了雙極型晶體管和場效應晶體管的圖示。,10,2,This figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P-N

8、 doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.,它們用于電路圖中的符號,當小電流注入基極時，可使較大的電流從集電極流向發(fā)射極。,11,2,The FET shown is an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. Whe

9、n a voltage is applied to the insulated gate terminal, a current is enabled to flow from the drain to the source. It is called N-channel, because the gate voltage induces an N-channel within the substrate, enabling current to flow between the N-regions.,將電壓加在絕緣的柵極上時，可使電流由漏極流向源極。,因為柵極電壓誘導基底上的N通道，使電流能

10、在兩個N區(qū)域之間流動。,12,3,Another basic semiconductor structure shown in Figure 2.1 is a diode, which is formed simply by a junction of N-type and P-type silicon. Diodes act like one-way valves by conducting current only from P to N.,二極管的作用就像一個單向閥門，由于電流只能從P流向N。,13,3,Special diodes can be created that emit li

11、ght when a voltage is applied. Appropriately enough, these components are called light emitting diodes, or LEDs. These small lights are manufactured by the millions and are found in diverse applications from telephones to traffic lights.,這種小燈泡數(shù)以百萬計地被制造出來，有各種各樣的應用，從電話機到交通燈。,14,4,The resulting small c

12、hip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the outside world.4,半導體材料上制作晶體管或二極管所形成的小芯片用塑料封裝以防損傷和被外界污染。,15,4,Small wires are connected within this package between the semicond

13、uctor sandwich and pins that protrude from the package to make electrical contact with other parts of the intended circuit.,從封裝內(nèi)伸出以便與（使用該晶體管的）電路其余部分連接。,16,4,Once you have several discrete transistors, digital logic can be built by directly wiring these components together. The circuit will function,

14、 but any substantial amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates.,任何實質(zhì)性的數(shù)字邏輯（電路）都將十分龐大，因為要在各種邏輯門中每實現(xiàn)一種都需要多個晶體管。,17,5,At the time of the invention of the transistor in 1947 by John Bardeen, Walter Brattain,

15、 and William Shockley, the only way to assemble multiple transistors into a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a means of fabricating multiple transistors on a single slab of semiconductor materi

16、al.,購買多個分離的晶體管，將它們連在一起。,一種將多個晶體管做在同一片半導體材料上的方法,18,5,Their invention would come to be known as the integrated circuit, or IC, which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors and diodes onto the same small semiconductor chip. Inst

17、ead of having to solder individual wires between discrete components, an IC contains many small components that are already wired together in the desired topology to form a circuit.,IC包含按照形成電路所要求的拓撲結(jié)構(gòu)連在一起的許多小元件，而無需再將分立元件的導線焊接起來。,19,6,A typical IC, without its plastic or ceramic package, is a square

18、or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used to manufacture the IC, there may be anywhere from a dozen to tens of millions of individual transistors on this small chip.,每一邊2mm至15mm的方形或矩形硅片,在這種小片上可能有幾十個到幾百萬個晶體管,20,6,This amazing density of

19、 electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in units of micrometers, with one micrometer (1mm) being one millionth of a meter. To serve as a reference point, a human hair is roughly 100mm in diame

20、ter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm!,1微米是1米的百萬分之一,21,6,Each year, researchers and engineers have been finding new ways to steadily reduce these feature sizes to pack more transistors into the same silicon area, as indicated in Figure 2.

21、2.,22,7,When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes create BJTs, whereas MOS processes create FETs. Bipolar logic was more common before the 1980s, but MOS technologies have since a

22、ccounted the great majority of digital logic ICs.,此后MOS技術在數(shù)字邏輯集成電路中占據(jù)了大多數(shù),23,7,N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, complementary-MOS, or CMOS, became the dominant process technology and remains so to this day. CMOS ICs

23、incorporate both NMOS and PMOS transistors.,占主導地位的加工技術,Part II,Application Specific Integrated Circuit,25,New Words,26,New Words,27,New Words,28,1,An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose

24、 use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications.,而不是通用的,7400與4000系列集成電路是可以用導線連接的邏輯構(gòu)建模塊，適用于各種不同的應用,29,2,As feature siz

25、es have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.1,隨著逐年來特征尺寸的縮小和設計工具的改進，ASIC中的最大復雜度從5000個門電路增長到了1億個門電路，因而功能也有極大的提高。,30,2,Modern ASICs often include entire 32-bit processors, me

26、mory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.,現(xiàn)代ASIC常包含32位處理器，包括ROM、RAM、EEPROM、

27、Flash等存儲器，以及其它大規(guī)模組件。,31,3,Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lowe

28、r production volumes, FPGAs may be more cost effective than an ASIC design.,7400系列和面包板的現(xiàn)代版,較小規(guī)模的設計或（與）小批量生產(chǎn),32,3,The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.2,不能循環(huán)的工程費用（建立工廠生產(chǎn)特定ASIC的成本）可能會達到數(shù)十萬美元。,33,4,

29、The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.3,專用集成電路這一通用名詞也包括FPGA，但是大多數(shù)設計者僅將ASIC用于非現(xiàn)場可編程的器件，將ASIC和FPGA兩者區(qū)別開來。,34,5 History,The initial ASICs used gate array

30、technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized

31、by both metal and polysilicon layers. Some base dies include RAM elements.,多至幾千個門電路的復雜度,適應用戶的包含金屬和多層硅的不同基底,35,6 Standard cell design,In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party desi

32、gn tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.4,盡管有第三方設計工具，但第三方設計工具和不同的ASIC制造商的布線以及實際半導體工藝過程的性能之間卻缺乏有效的聯(lián)系。,36,6,Most designers ended up using fact

33、ory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation de

34、lay, capacitance and inductance; that could also be represented in third party tools.5,每個ASIC制造商都可創(chuàng)造他們自己的具有已知電性能的功能塊，如傳播延遲器、電容、電感，這些都可以用第三方工具來表示（實現(xiàn)）。,37,6,Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard ce

35、ll design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.6,標準單元設計使門陣列和全定制設計之間在一次性投入的工程費用和循環(huán)元件成本方面相互適應。,Non-recurring engineering (NRE) refers to the one-time cost of researching, designing, and testing a new product.,3

36、8,7,By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual s

37、tages, although these stages overlap significantly in practice.,標準單元集成電路的設計過程在概念上需經(jīng)過以下幾個過程，但事實上在實際生產(chǎn)中這些工序都有較大的重疊。,39,8,These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later int

38、roduced by the physical fabrication process.7,以工業(yè)界普通的熟練水平實現(xiàn)的這些步驟幾乎總是產(chǎn)生能正確實現(xiàn)原設計的最終器件，除非后來在物理制造過程中引入了缺陷。,40,9,A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis.,對新的ASIC所要求功能的非正式理解,41,9,The design team

39、constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register transfer level) design.,這一過程可類比于用高級語言編寫計算機程序,42,9,Suitability for purpose is verified by simulation. A v

40、irtual system created in software, using a tool such as Virtutechs Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second.,以高達每秒數(shù)十億條模擬指令的速度來模擬ASIC的功能,43,9,A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large coll

41、ection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.8,這些構(gòu)成的元素是從一個標準單元庫中得到的，這個庫由事先規(guī)定好的門電路集合構(gòu)成，例如2輸入或非門，2輸入與非門，非門等等。,44,9,The standard cell

42、s are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.,所產(chǎn)生的所有標準單元加上連接他們所需要的導線稱為門級網(wǎng)表。,45,9,The gate-level netlist is next processed by a placement tool which pla

43、ces the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement.,將標準單元布局在代表最終ASIC的區(qū)域,服從各種規(guī)定的約束,46,9,The rou

44、ting tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling semicondu

45、ctor fabrication to produce physical ICs.,由于搜索空間很大，該過程將產(chǎn)生滿足充分條件的解，而不是全局最優(yōu)解。,47,9,Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are

46、 used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication.,這一測試表明器件將在所有極端的過程、電壓、溫度下正常工作。,48,10,These design s

47、teps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturers cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design.9,重要的差別在于標準單元設計使用制造商的單

48、元庫，這些庫已用于數(shù)以百計的設計實現(xiàn)，因而比起全定制設計來風險小得多。,49,11 Gate array design,Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.10,

49、門陣列設計是一種制造方法，事先定義好擴散層（晶體管和其它有源器件），包含這些器件的晶片在金屬化之前被庫存，就是說先不進行聯(lián)接。,50,11,The physical design process then defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Ga

50、te array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization.11,門陣列ASIC是一種折中方案，因為將某一給定的設計與制造商庫存的晶片相對應總是不可能達到100%利用率的。,51,12,Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost enti

51、rely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.12,現(xiàn)在電路設計者已經(jīng)很少采用純粹的邏輯門陣列設計，而幾乎都代之以FPGA之類的現(xiàn)場可編程器件了。這些器件可由用戶編程，使工具作業(yè)費用最低，以略為提高的零件價格獲得可比的性能。,52,12,Today gate arr

52、ays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.13,現(xiàn)在門陣列正在發(fā)展為結(jié)構(gòu)化ASIC，其中包含很大的IP內(nèi)核，如處理器、DSP單元、外圍設備、標準接口、集成SRAM存儲器、以及一組可重新設置的未確定功能的邏輯單元。,IP core

53、 (intellectual property core)：預先設計好，可復用，有知識產(chǎn)權的硬件或軟件塊,53,12,This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic blocks.,片上系統(tǒng)所要求的（功能）比僅僅邏輯單元多得多,54,13 Full-custom design,The benefits of

54、full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip.,減小的面積，性能的改進，以及集成模擬元件和其他預先設計的元件,55,13,The disadvantages can include increased manufa

55、cturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.14,缺點包括增加的制造和設計時間，增加的不可循環(huán)工程成本，更復雜的CAD系統(tǒng)，和對設計團隊熟練程度高得多的要求。,56,13,However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any perform