1、計(jì)數(shù)顯示電路設(shè)計(jì)一 設(shè)計(jì)要求設(shè)計(jì)輸出為3位BCD碼的計(jì)數(shù)顯示電路。由三個(gè)模塊構(gòu)成：十進(jìn)制計(jì)數(shù)器（BCD_CNT）、分時(shí)總線切換電路（SCAN）和七段顯示譯碼器電路（DEC_LED）。BCD碼計(jì)數(shù)電路從0計(jì)到9然后返回到0從新計(jì)數(shù)。3位BCD碼計(jì)數(shù)器可以實(shí)現(xiàn)從0到999的十進(jìn)制計(jì)數(shù)。要將計(jì)數(shù)過程用七段顯示LED數(shù)碼管顯示出來，這里采用動(dòng)態(tài)分時(shí)總線切換電路對(duì)數(shù)碼管進(jìn)行掃描，對(duì)數(shù)碼管依次分時(shí)選中進(jìn)行輸出計(jì)數(shù)的個(gè)、十、百位的數(shù)據(jù)?？驁D如圖1：圖1二 設(shè)計(jì)思路圖2是源程序的RTL級(jí)電路圖。整個(gè)設(shè)計(jì)分十進(jìn)制計(jì)數(shù)器模塊（BCD_CNT）、分時(shí)總線切換電路模塊（SCAN）和七段顯示譯碼器電路模塊（DEC_LE

2、D）構(gòu)成?？偟妮斎霝槭M(jìn)制計(jì)數(shù)器時(shí)鐘clk，異步復(fù)位清零信號(hào)reset，分時(shí)總線切換電路時(shí)鐘CL。在reset信號(hào)為0期間，在每個(gè)clk的上升沿計(jì)數(shù)器將加1。在每個(gè)cl的上升沿將會(huì)改變對(duì)三個(gè)數(shù)碼管的掃描選通?？偟妮敵鰹閿?shù)碼管選通信號(hào)sel（三位），輸出到七段數(shù)碼管的數(shù)據(jù)信號(hào)ledout（七位）。圖2為了檢驗(yàn)系統(tǒng)的正確與否，這里還添加了四個(gè)輸出：十進(jìn)制計(jì)數(shù)器輸出c1（四位）、c2（四位）、c3（四位），分時(shí)總線切換電路一個(gè)輸出q（四位），它是對(duì)計(jì)數(shù)器輸出c1、c2、c3進(jìn)行分時(shí)輸出。分時(shí)選通個(gè)、十、百位的數(shù)碼管并將相應(yīng)要顯示的數(shù)據(jù)輸出到七段顯示譯碼器電路（DEC_LED），由此實(shí)現(xiàn)數(shù)碼管的動(dòng)態(tài)掃

3、描顯示。三 VHDL源代碼（1）頂層模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top isport(clk,reset:in std_logic; CL:in std_logic; c1,c2,c3:out std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0); q:out std_logic_vector(3 downto 0)

4、; sel:out std_logic_vector(2 downto 0);end top;architecture content of top issignal c1_1,c2_1,c3_1:std_logic_vector(3 downto 0);signal q_1:std_logic_vector(3 downto 0);component BCD_CNT is port(clk,reset:in std_logic; c1,c2,c3:out std_logic_vector(3 downto 0);end component;component SCAN isport( c1,

5、c2,c3:in std_logic_vector(3 downto 0); CL:in std_logic; q:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0);end component;component DEC_LED isport( q:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0);end component;beginu1: BCD_CNT port map (clk,reset,c1_1,

6、c2_1,c3_1); u2: SCAN port map(c1_1,c2_1,c3_1,CL,q_1,sel); u3: DEC_LED port map(q_1,ledout);c1=c1_1;c2=c2_1;c3=c3_1;q =q_1; end content;（2）十進(jìn)制計(jì)數(shù)器電路（BCD_CNT）模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity BCD_CNT is port(clk,reset:in std_

7、logic; c1,c2,c3:out std_logic_vector(3 downto 0);end BCD_CNT;architecture cnt of BCD_CNT issignal cn1,cn2,cn3:std_logic_vector(3 downto 0); begin cnt1:process(clk,reset) begin if(reset=1) then cn1=0000; elsif(clkevent and clk=1) then if(cn19) then cn1=cn1+1; else cn1=0000; end if; end if; end proces

8、s cnt1; c1=cn1; cnt2:process(cn1(3),reset) begin if(reset=1) then cn2=0000; elsif(cn1(3)event and cn1(3)=0) then if(cn29) then cn2=cn2+1; else cn2=0000; end if; end if; end process cnt2; c2=cn2; cnt3:process(cn2(3),reset) begin if(reset=1) then cn3=0000; elsif(cn2(3)event and cn2(3)=0) then if(cn39)

9、 then cn3=cn3+1; else cn3=0000; end if; end if; end process cnt3; c3=cn3; end cnt;（3）分時(shí)總線切換電路（SCAN）模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity SCAN is port( c1,c2,c3:in std_logic_vector(3 downto 0); cl:in std_logic; q:out std_logic_

10、vector(3 downto 0); sel:out std_logic_vector(2 downto 0); end SCAN;architecture one of SCAN issignal cnt:std_logic_vector(1 downto 0);signal q_temp:std_logic_vector(3 downto 0);signal sel_temp:std_logic_vector(2 downto 0); beginp1:process(cl)begin if(clevent and cl=1) then if(cnt2) then cnt=cnt+1; else cnt q_temp=c1; sel_temp q_temp=c2; sel_temp q_temp=c3; sel_temp null; end case; end process p2; q=q_temp; sel ledout ledout ledout ledout ledout ledout ledout ledout ledout ledout null; end case; end process;end one; 四 仿真結(jié)果圖2是電路的總體輸入輸出仿真波形。圖3五、結(jié)果分析由圖3可以看出，當(dāng)掃描頻率CL很大的時(shí)候，sel