1、2009級(jí)數(shù)字電路實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)名稱： EDA基礎(chǔ)實(shí)驗(yàn)學(xué)生姓名： 桂柯易班 級(jí)： 2009211120班內(nèi)序號(hào)： 07學(xué) 號(hào)： 09210580日 期： 2011年4月28日1.實(shí)驗(yàn)要求【實(shí)驗(yàn)?zāi)康摹?.熟悉用QuartusII原理圖輸入法進(jìn)行電路設(shè)計(jì)和仿真；2.掌握QuartusII圖形模塊單元的生成與調(diào)用；3.熟悉用VHDL語(yǔ)言設(shè)計(jì)組合邏輯電路和時(shí)序電路的方法；4.熟悉用QuartusII文本輸入法和圖形輸入法進(jìn)行電路設(shè)計(jì)；5.熟悉不同的編碼及其之間的轉(zhuǎn)換；6.掌握觸發(fā)器的邏輯功能及使用方法；7.熟悉計(jì)數(shù)器、寄存器、鎖存器、分頻器、移位寄存器的設(shè)計(jì)方法8.掌握VHDL語(yǔ)言的語(yǔ)法規(guī)范，掌握時(shí)序電

2、路描述方法；9.掌握多個(gè)數(shù)碼管動(dòng)態(tài)掃描顯示的原理及設(shè)計(jì)方法?！緦?shí)驗(yàn)所用儀器及元器件】 1.計(jì)算機(jī) 2.直流穩(wěn)壓電源 3.數(shù)字系統(tǒng)與邏輯設(shè)計(jì)實(shí)驗(yàn)開發(fā)板【實(shí)驗(yàn)內(nèi)容】 1.用邏輯門設(shè)計(jì)實(shí)現(xiàn)一個(gè)半加器，仿真驗(yàn)證其功能，并生成新的半加器圖形模塊單元。 2.用實(shí)驗(yàn)內(nèi)容1中生成的半加器模塊和邏輯門設(shè)計(jì)實(shí)現(xiàn)一個(gè)全加器，仿真驗(yàn)證其功 能，并下載到實(shí)驗(yàn)板測(cè)試，要求用撥碼開關(guān)設(shè)定輸入信號(hào)，發(fā)光二極管顯示輸出信 號(hào)。 3.用3線-8線譯碼器（74LS138）和邏輯門設(shè)計(jì)實(shí)現(xiàn)函數(shù)F，仿真驗(yàn)證其功能，并下 載到實(shí)驗(yàn)板測(cè)試。要求用撥碼開關(guān)設(shè)定輸入信號(hào)，發(fā)光二極管顯示輸出信號(hào)。 4.用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)3位二進(jìn)制數(shù)值比

3、較器，仿真驗(yàn)證其功能，并下載到實(shí) 驗(yàn)板測(cè)試。要求用撥碼開關(guān)設(shè)定輸入信號(hào)，發(fā)光二極管顯示輸出信號(hào)。 5.用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)4選1的數(shù)據(jù)選擇器；一個(gè)8421碼轉(zhuǎn)換為格雷碼的代碼 轉(zhuǎn)換器；一個(gè)舉重比賽裁判器；一個(gè)帶同步置位和同步復(fù)位功能的D觸發(fā)器；一個(gè) 帶異步復(fù)位的4位二進(jìn)制減計(jì)數(shù)器；一個(gè)帶異步復(fù)位的8421碼十進(jìn)制計(jì)數(shù)器；一 個(gè)帶異步復(fù)位的4位自啟動(dòng)環(huán)形計(jì)數(shù)器；一個(gè)帶控制端的8位二進(jìn)制寄存器，當(dāng)控 制端為1時(shí)，電路正常工作，否則輸出為高阻態(tài)；一個(gè)分頻系數(shù)為12，分頻輸 出信號(hào)占空比為50%的分頻器。仿真驗(yàn)證其功能，并下載到實(shí)驗(yàn)板測(cè)試。要求用撥 碼開關(guān)和按鍵開關(guān)設(shè)定輸入信號(hào)，發(fā)光二極管顯示輸

4、出信號(hào)。（注：有幾個(gè)不需要 下載到實(shí)驗(yàn)板測(cè)試）2.程序分析全加器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder IS PORT(a,b:IN STD_LOGIC; co,so:OUT STD_LOGIC);END ENTITY h_adder;ARCHITECTURE a OF h_adder ISBEGIN so<= a XOR b; co<= a AND b;END;library ieee;use ieee.std_logic_1164.all;entity GKY07P3 is port(ain,bin,ci

5、n:in std_logic; cout,sum:out std_logic);end entity GKY07P3;architecture a of GKY07P3 iscomponent h_adder port(a,b:in std_logic; co,so:out std_logic);end component;signal d,e,f:std_logic;begin u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2:h_adder port map(a=>e,b=>cin,co=>f,s

6、o=>sum); cout<=d or f;end;整體思路是按照實(shí)驗(yàn)的要求，先做出一個(gè)半加器，然后在這個(gè)半加器的基礎(chǔ)上實(shí)現(xiàn)全加器的功能。函數(shù)F：3位二進(jìn)制數(shù)值比較器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P4 IS PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC);END GKY07P4;ARCHITECTURE behave OF GKY07P4 ISBEGIN P

7、ROCESS(A,B) BEGIN IF(A>B)THEN YA<='1'YB<='0'YC<='0' ELSIF(A<B)THEN YA<='0'YB<='1'YC<='0' ELSE YA<='0'YB<='0'YC<='1' END IF; END PROCESS;END behave;將比較的過(guò)程直接交給軟件本身，只需通過(guò)不同的二進(jìn)制數(shù)輸出比較的結(jié)果即可。4選1數(shù)據(jù)選擇器：LIB

8、RARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P5 IS PORT(G,A1,A0:IN STD_LOGIC; D0,D1,D2,D3:IN STD_LOGIC; Y,YB:OUT STD_LOGIC);END GKY07P5;ARCHITECTURE behave OF GKY07P5 IS SIGNAL comb:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN comb<=A1&A0; PROCESS(G,comb,D0,D1,D2,D3) BEGIN IF G='0'THEN CAS

9、E comb IS WHEN"00"=>Y<=D0;YB<= NOT D0; WHEN"01"=>Y<=D1;YB<= NOT D1; WHEN"10"=>Y<=D2;YB<= NOT D2; WHEN"11"=>Y<=D3;YB<= NOT D3; WHEN OTHERS=>Y<='0'YB<='1' END CASE; ELSE Y<='0'YB<='1&

10、#39; END IF; END PROCESS;END behave;主要是WHEN語(yǔ)句的運(yùn)用，用兩位二進(jìn)制數(shù)表示四種數(shù)據(jù)輸出狀態(tài)，再用WHEN語(yǔ)句具體實(shí)現(xiàn)。8421碼轉(zhuǎn)換為格雷碼：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P6 IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END GKY07P6;ARCHITECTURE behave OF GKY07P6 ISBEGIN PROCESS(A) BEGIN B(3)&l

11、t;=A(3); B(2)<=A(3) XOR A(2); B(1)<=A(2) XOR A(1); B(0)<=A(1) XOR A(0); END PROCESS;END behave;本來(lái)是考察WHEN語(yǔ)句的運(yùn)用，將所有的情況用WHEN語(yǔ)句列出來(lái)，但是因?yàn)?421碼轉(zhuǎn)換為格雷碼的時(shí)候有一個(gè)相關(guān)的計(jì)算式子，采用這個(gè)式子可以使程序簡(jiǎn)化不少。舉重比賽裁判器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P7 IS PORT(a:IN STD_LOGIC_VECTOR(2 DOWNTO 0); b:OUT STD_LO

12、GIC_VECTOR(2 DOWNTO 0);END GKY07P7;ARCHITECTURE behave OF GKY07P7 ISBEGIN PROCESS(a) BEGIN CASE a IS WHEN"000" => b <= "000" WHEN"001" => b <= "000" WHEN"010" => b <= "000" WHEN"011" => b <= "100"

13、 WHEN"100" => b <= "100" WHEN"101" => b <= "111" WHEN"110" => b <= "111" WHEN"111" => b <= "111" END CASE; END PROCESS;END;與前幾題不同，這個(gè)更偏向應(yīng)用。列出實(shí)際情況的狀態(tài)表，發(fā)現(xiàn)三個(gè)裁判的不同判斷各對(duì)應(yīng)紅黃綠燈的亮滅情況，故還是WHEN語(yǔ)句的應(yīng)用。D觸發(fā)器：LIBRA

14、RY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P8 IS PORT(d,clk,set,reset:IN STD_LOGIC; q,qb:OUT STD_LOGIC);END GKY07P8;ARCHITECTURE struc OF GKY07P8 ISBEGIN PROCESS(clk,set,reset) BEGIN IF set='0' AND reset='1' THEN q<='1'qb<='0' ELSIF set='1' AND rese

15、t='0' THEN q<='0'qb<='1' ELSIF clk'EVENT AND clk='1' THEN q<=d;qb<=NOT d; END IF; END PROCESS;END struc; 和書上的例子基本一樣，只是同步置位和同步復(fù)位都跟隨時(shí)間脈沖的變化。4位二進(jìn)制減計(jì)數(shù)器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P9 IS PORT(clk,rese

16、t:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END GKY07P9;ARCHITECTURE struc OF GKY07P9 IS SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF reset='0'THEN q_temp<="1111" ELSIF q_temp<="0000" THEN q_

17、temp<="1111" ELSE q_temp<=q_temp-1; END IF; END IF; END PROCESS; q<=q_temp;END struc;從狀態(tài)1111到狀態(tài)0000，然后再跳回1111。異步復(fù)位不需要跟隨脈沖變化，要立即復(fù)位。8421碼十進(jìn)制計(jì)數(shù)器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P10 IS PORT(clk,reset:IN STD_LOGIC; q:OUT STD_LOGIC_VE

18、CTOR(3 DOWNTO 0);END GKY07P10;ARCHITECTURE struc OF GKY07P10 IS SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF reset='1'THEN q_temp<="0000" ELSIF q_temp="1001"THEN q_temp<="0000" ELSE q_temp

19、<=q_temp+1; END IF; END IF; END PROCESS; q<=q_temp;END struc; 從狀態(tài)0000到狀態(tài)1001，然后再跳回0000，異步復(fù)位要立即復(fù)位。4位環(huán)形計(jì)數(shù)器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P11 IS PORT(clk,reset:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END GKY07P11;ARCHITECTURE behave OF GKY07P11 IS SIGNAL nex

20、tcount: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,reset) BEGIN IF RESET='1' THEN nextcount<="0001" ELSIF(clk'EVENT AND clk='1')THEN CASE nextcount IS WHEN"0001"=> nextcount <="0010" WHEN"0010"=> nextcount <="0100&qu

21、ot; WHEN"0100"=> nextcount <="1000" WHEN OTHERS=>nextcount<="0001" END CASE; END IF; END PROCESS; countout<=nextcount;END behave;計(jì)數(shù)狀態(tài)在0001，0010，0100，1000四個(gè)之間轉(zhuǎn)換，由于需要能夠自啟動(dòng)，對(duì)別狀態(tài)的處理是全部引到那四個(gè)計(jì)數(shù)狀態(tài)上。8位二進(jìn)制寄存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY GKY07P1

22、2 IS PORT(d:IN STD_LOGIC_VECTOR(7 DOWNTO 0); oe,clk:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END GKY07P12;ARCHITECTURE struc OF GKY07P12 IS SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(clk,oe) BEGIN IF oe='1' THEN IF clk'EVENT AND clk='1' THEN temp<=d; END IF

23、; ELSE temp<="ZZZZZZZZ" END IF; q<=temp; END PROCESS;END struc;和書上的例子基本一樣，將低電平控制改成高電平控制即可。分頻器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P13 IS PORT(clk,clear:IN STD_LOGIC; clk_out:OUT STD_LOGIC);END GKY07P13;ARCHITECTURE struc OF GKY07P13 IS

24、 SIGNAL temp:INTEGER RANGE 0 TO 11;BEGIN p1:PROCESS(clear,clk) BEGIN IF clear='0' THEN temp<=0; ELSIF clk'EVENT AND clk='1' THEN IF temp=11 THEN temp<=0; ELSE temp<=temp+1; END IF; END IF; END PROCESS p1; p2:PROCESS(temp) BEGIN IF temp<6 THEN clk_out<='0' E

25、LSE clk_out<='1' END IF; END PROCESS p2;END struc;很重要的一個(gè)器件，但是設(shè)計(jì)難度并不很高，首先是模為12的計(jì)數(shù)，然后是占空比50%。數(shù)碼管串行掃描電路：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P14 IS PORT(clk,clear:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); countout:OUT STD_LOGIC_VECTOR(5

26、 DOWNTO 0);END GKY07P14;ARCHITECTURE behave OF GKY07P14 IS SIGNAL q_temp:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL cnt:INTEGER RANGE 0 TO 5;BEGIN p1:PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF(cnt=5)THEN cnt<=0; ELSE cnt<=cnt+1; END IF;

27、 END IF; END PROCESS; p2:PROCESS(cnt) BEGIN IF(clear='0')THEN count<="111111" ELSE CASE cnt IS WHEN 1=>count<="101111"q_temp<="0110000" WHEN 2=>count<="110111"q_temp<="1101101" WHEN 3=>count<="111011"q_tem

28、p<="1111001" WHEN 4=>count<="111101"q_temp<="0110011" WHEN 5=>count<="111110"q_temp<="1011011" WHEN 0=>count<="011111"q_temp<="1111110" END CASE; END IF; END PROCESS; countout<=count; q<=q_temp;

29、END behave; 先用05六進(jìn)制計(jì)數(shù)器產(chǎn)生六個(gè)計(jì)數(shù)狀態(tài)，這六個(gè)狀態(tài)同時(shí)決定二極管點(diǎn)亮的數(shù)字和數(shù)碼管接通的電路，在時(shí)鐘信號(hào)頻率很高的時(shí)候可以同時(shí)顯示05六個(gè)數(shù)字。只是在下載到實(shí)驗(yàn)板的時(shí)候與芯片的各個(gè)引腳一定要對(duì)應(yīng)，不然容易達(dá)不到實(shí)驗(yàn)要求。數(shù)碼管滾動(dòng)顯示電路：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P14 IS PORT( clk,clear:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); countout:OU

30、T STD_LOGIC_VECTOR(5 DOWNTO 0);END GKY07P14;ARCHITECTURE behave OF GKY07P14 IS SIGNAL q_temp:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL cnt,cnt1:INTEGER RANGE 0 TO 5; SIGNAL tmp:INTEGER RANGE 0 TO 1999; signal clk1:STD_LOGIC;BEGIN p0:PROCESS(clk,clear) BEGIN IF c

31、lear='0' THEN tmp<=0; ELSIF clk'EVENT AND clk='1' THEN IF tmp=1999 THEN tmp<=0; ELSE tmp<=tmp+1; END IF; END IF; END PROCESS p0; p1:PROCESS(tmp) BEGIN IF clk'EVENT AND clk='1' THEN IF tmp<1000 THEN clk1<='0' ELSE clk1<='1' END IF; END

32、 IF; END PROCESS p1; p2:PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF(cnt=5)THEN cnt<=0; ELSE cnt<=cnt+1; END IF; END IF; END PROCESS p2; p3:PROCESS(clk1) BEGIN IF(clk1'EVENT AND clk1='1')THEN IF(cnt1=5)THEN cnt1<=0; ELSE cnt1<=cnt1+1; END IF; END IF; END PR

33、OCESS p3; p4:PROCESS(cnt,cnt1) BEGIN IF(clear='0')THEN q_temp<="0000000" ELSE CASE cnt+cnt1 IS WHEN 0=>q_temp<="1111110" WHEN 1=>q_temp<="0110000" WHEN 2=>q_temp<="1101101" WHEN 3=>q_temp<="1111001" WHEN 4=>q_tem

34、p<="0110011" WHEN 5=>q_temp<="1011011" WHEN 6=>q_temp<="1111110" WHEN 7=>q_temp<="0110000" WHEN 8=>q_temp<="1101101" WHEN 9=>q_temp<="1111001" WHEN 10=>q_temp<="0110011" WHEN 11=>q_temp<

35、;="1011011" WHEN OTHERS =>q_temp<="0000000" END CASE; END IF; END PROCESS p4; q<=q_temp; p5:PROCESS(cnt) BEGIN IF(clear='0')THEN count<="111111" ELSE CASE cnt IS WHEN 0=>count<="011111" WHEN 1=>count<="101111" WHEN 2=&

36、gt;count<="110111" WHEN 3=>count<="111011" WHEN 4=>count<="111101" WHEN 5=>count<="111110" WHEN OTHERS =>count<="111111" END CASE; END IF; END PROCESS p5; countout<=count;END behave; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.

37、ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY GKY07P14 IS PORT( clk,clear:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); countout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END GKY07P14;ARCHITECTURE behave OF GKY07P14 IS SIGNAL q_temp:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0); SI

38、GNAL cnt,cnt1:INTEGER RANGE 0 TO 11; SIGNAL tmp:INTEGER RANGE 0 TO 1999; signal clk1:STD_LOGIC;BEGIN p0:PROCESS(clk,clear) BEGIN IF clear='0' THEN tmp<=0; ELSIF clk'EVENT AND clk='1' THEN IF tmp=1999 THEN tmp<=0; ELSE tmp<=tmp+1; END IF; END IF; END PROCESS p0; p1:PROCES

39、S(tmp) BEGIN IF clk'EVENT AND clk='1' THEN IF tmp<1000 THEN clk1<='0' ELSE clk1<='1' END IF; END IF; END PROCESS p1; p2:PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF(cnt=11)THEN cnt<=0; ELSE cnt<=cnt+1; END IF; END IF; END PROCESS p2; p3:P

40、ROCESS(clk1) BEGIN IF(clk1'EVENT AND clk1='1')THEN IF(cnt1=11)THEN cnt1<=0; ELSE cnt1<=cnt1+1; END IF; END IF; END PROCESS p3; p4:PROCESS(cnt,cnt1) BEGIN IF(clear='0')THEN q_temp<="0000000" ELSE CASE cnt+cnt1 IS WHEN 6=>q_temp<="1111110" WHEN 7=

41、>q_temp<="0110000" WHEN 8=>q_temp<="1101101" WHEN 9=>q_temp<="1111001" WHEN 10=>q_temp<="0110011" WHEN 11=>q_temp<="1011011" WHEN OTHERS =>q_temp<="0000000" END CASE; END IF; END PROCESS p4; q<=q_temp; p5:PROCESS(cnt) BEGIN IF(clear=&