先進(jìn)芯片封裝知識(shí)介紹課件_第1頁(yè)
先進(jìn)芯片封裝知識(shí)介紹課件_第2頁(yè)
先進(jìn)芯片封裝知識(shí)介紹課件_第3頁(yè)
先進(jìn)芯片封裝知識(shí)介紹課件_第4頁(yè)
先進(jìn)芯片封裝知識(shí)介紹課件_第5頁(yè)
已閱讀5頁(yè)，還剩63頁(yè)未讀， 繼續(xù)免費(fèi)閱讀

下載本文檔

版權(quán)說明：本文檔由用戶提供并上傳，收益歸屬內(nèi)容提供方，若內(nèi)容存在侵權(quán)，請(qǐng)進(jìn)行舉報(bào)或認(rèn)領(lǐng)

文檔簡(jiǎn)介

先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage22020/11/30先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹1OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage2020/11/302OutlinePackageDevelopmentTrePackageDevelopmentTrend2020/11/303PackageDevelopmentTrend2020/SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend2020/11/304SOFamilyQFPFamilyBGAFamilyPCSPFamilyMemoryCardSiPModulePackageDevelopmentTrend2020/11/305CSPFamilyMemoryCardSiPModul3DPackage3DPackage2020/11/3063DPackage3DPackage2020/11/303DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP

3S-CSPS-etCSPetCSP+S-CSP

PS-fcCSP+SCSP

PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP

5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2

PoPQFN4SS-SCSP2020/11/3073DPackageIntroductionetCSPSStackedDieTopdieBottomdieFOWmaterilWire2020/11/308StackedDieTopdieBottomdieFOTSVTSV(ThroughSiliconVia) Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV2020/11/309TSVTSV(ThroughSiliconVia)WiWhat’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.

PoP2020/11/3010What’sPoP?PoP2020/11/3010PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology2020/11/3011PoPPS-vfBGAPS-etCSPLowLoopWiPoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV?PoPTopviewBottomviewThroughMoldVia2020/11/3012PoPAllowsforwarpagereductioPoP

BallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP2020/11/3013PoPBallPlacementontopsurfDigital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP2020/11/3014Digital(Btmdie)+Analog(MiddEasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?

PiP2020/11/3015EasysystemintegrationIthasMaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology

PiP2020/11/3016MaterialforHighReliabilityMemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP

2020/11/3017MemoryPKGSubstrateFlipchipMeWLCSP&FlipChipPackage2020/11/3018WLCSP&FlipChipPackage2020/WLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.

WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.2020/11/3019WLCSPWhatisWLCSP?2020/11/301WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.2020/11/3020WLCSPWhyWLCSP?2020/11/3020RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.

Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).2020/11/3021RDLRDL:RedistributionLayer20WLCSPProcessFlowofWLCSP2020/11/3022WLCSPProcessFlowofWLCSP2020WLCSPProcessFlowofWLCSP2020/11/3023WLCSPProcessFlowofWLCSP2020FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)2020/11/3024FlipChipPackageFCBGA(PI)-EHSBump2020/11/3025Bump2020/11/3025BumpDevelopment2020/11/3026BumpDevelopment2020/11/3026BumpDevelopment2020/11/3027BumpDevelopment2020/11/3027BumpDevelopment2020/11/3028BumpDevelopment2020/11/3028C4FlipChipWhat’sC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold2020/11/3029C4FlipChipWhat’sC4FlipChiC4FlipChipBGAMainFeaturesBallPitch:0.4mm-1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912

TargetMarket:

CPU、FPGA、Processor、Chipset、Memory、Router、Switches、andDSPetc.MainBenefits

ReducedSignalInductanceReducedPower/GroundInductanceHigherSignalDensityDieShrink&ReducedPackageFootprintHighSpeedandHighthermalsupport2020/11/3030C4FlipChipBGAMainFeaturesC2FlipChipWhat’sC2FlipChip?C2is:ChipConnectionChipisconnectedtosubstratebycopperpostBumpmaterialtype:copperpostwithsolderplatingSiliconDieCopperpostSolder2020/11/3031C2FlipChipWhat’sC2FlipChiC2FlipChipProcessFlowofC22020/11/3032C2FlipChipProcessFlowofC2C2FlipChipComparison:C2VsC4 Insomecases,C2canreplaceC4orwirebondingpackage.2020/11/3033C2FlipChipComparison:C2Vs謝謝！謝謝！34先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage22020/11/30先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹先進(jìn)芯片封裝知識(shí)介紹35OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage2020/11/3036OutlinePackageDevelopmentTrePackageDevelopmentTrend2020/11/3037PackageDevelopmentTrend2020/SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend2020/11/3038SOFamilyQFPFamilyBGAFamilyPCSPFamilyMemoryCardSiPModulePackageDevelopmentTrend2020/11/3039CSPFamilyMemoryCardSiPModul3DPackage3DPackage2020/11/30403DPackage3DPackage2020/11/303DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP

3S-CSPS-etCSPetCSP+S-CSP

PS-fcCSP+SCSP

PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP

5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2

PoPQFN4SS-SCSP2020/11/30413DPackageIntroductionetCSPSStackedDieTopdieBottomdieFOWmaterilWire2020/11/3042StackedDieTopdieBottomdieFOTSVTSV(ThroughSiliconVia) Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV2020/11/3043TSVTSV(ThroughSiliconVia)WiWhat’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.

PoP2020/11/3044What’sPoP?PoP2020/11/3010PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology2020/11/3045PoPPS-vfBGAPS-etCSPLowLoopWiPoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV?PoPTopviewBottomviewThroughMoldVia2020/11/3046PoPAllowsforwarpagereductioPoP

BallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP2020/11/3047PoPBallPlacementontopsurfDigital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP2020/11/3048Digital(Btmdie)+Analog(MiddEasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?

PiP2020/11/3049EasysystemintegrationIthasMaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology

PiP2020/11/3050MaterialforHighReliabilityMemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP

2020/11/3051MemoryPKGSubstrateFlipchipMeWLCSP&FlipChipPackage2020/11/3052WLCSP&FlipChipPackage2020/WLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.

WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.2020/11/3053WLCSPWhatisWLCSP?2020/11/301WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.2020/11/3054WLCSPWhyWLCSP?2020/11/3020RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.

Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).2020/11/3055RDLRDL:RedistributionLayer20WLCSPProcessFlowofWLCSP2020/11/3056WLCSPProcessFlowofWLCSP2020WLCSPProcessFlowofWLCSP2020/11/3057WLCSPProcessFlowofWLCSP2020FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-

溫馨提示

  • 1. 本站所有資源如無(wú)特殊說明，都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請(qǐng)下載最新的WinRAR軟件解壓。
  • 2. 本站的文檔不包含任何第三方提供的附件圖紙等，如果需要附件，請(qǐng)聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
  • 3. 本站RAR壓縮包中若帶圖紙，網(wǎng)頁(yè)內(nèi)容里面會(huì)有圖紙預(yù)覽，若沒有圖紙預(yù)覽就沒有圖紙。
  • 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
  • 5. 人人文庫(kù)網(wǎng)僅提供信息存儲(chǔ)空間，僅對(duì)用戶上傳內(nèi)容的表現(xiàn)方式做保護(hù)處理，對(duì)用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯，并不能對(duì)任何下載內(nèi)容負(fù)責(zé)。
  • 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容，請(qǐng)與我們聯(lián)系，我們立即糾正。
  • 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時(shí)也不承擔(dān)用戶因使用這些下載資源對(duì)自己和他人造成任何形式的傷害或損失。

最新文檔

評(píng)論

0/150

提交評(píng)論