...附錄2程序設(shè)置串行口波特率9600;串行口設(shè)置MODE1，SM1=0，REN=1,SMOD=1;晶振11.0592,定時(shí)設(shè)置為0FDH;常用端口設(shè)置參數(shù);FD9600;FA4800;F42400;E81200;;ORG00HJMPSTARTORG23HJMPUARTORG30HSTART:MOVSP,#70HMOVSCON,#50HMOVTMOD,#00100001B;TIM1在模式2TIM0在模式1MOVTH1,#0F4H;設(shè)置定時(shí)時(shí)間SETBTR1;啟動(dòng)定時(shí)器1SETBES;允許串口中斷SETBEA;允許總中斷MOVP0,#0;P0、P2輸出低電平JMP$;等待狀態(tài);*****************************************;串行口中斷;*****************************************UART:PUSHACCPUSHPSWCLRES;關(guān)閉串行口中斷MOVTH0,#HIGH(65536-65536)MOVTL0,#LOW(65536-65536)SETBTR0;開定時(shí)器0MOV30H,#00;同步位MOV31H,#00;數(shù)據(jù)1MOV32H,#00;數(shù)據(jù)2MOV33H,#00;結(jié)束位MOVR0,#30HREC:ctf0,FS;接收時(shí)間是否超時(shí)？是則執(zhí)行FSJNBRI,REC;接收數(shù)據(jù)CLRRIMOVA,SBUFMOVR0,AINCR0JMPRECFS:CLRTR0;關(guān)定時(shí)器0;********************************CALLFUN;解碼并控制繼電器SETBES;開串行口中斷POPPSWPOPACCRETI;中斷子程序返回;****************************************;解碼并控制繼電器;下面的程序可以更簡潔，但為了方便，展開來編制;****************************************FUN:MOVA,#0AH;判斷第1字節(jié)即同步位CJNEA,30H,ERRMOVA,#0DH;判斷第4字節(jié)即結(jié)束位CJNEA,33H,ERR;****************************************;第2字節(jié)即數(shù)據(jù)位1,代表繼電器J1-8;第3字節(jié)即數(shù)據(jù)位2,代表繼電器J9-16;****************************************MOVA,31HMOVP0,AMOVA,32HMOVP2,ARET;**************************************;數(shù)據(jù)錯(cuò)誤處理;**************************************ERR:MOV30H,#00;同步位MOV31H,#00;數(shù)據(jù)1MOV32H,#00;數(shù)據(jù)2MOV33H,#00;結(jié)束位RETEND;程序結(jié)束TheDescriptionofAT89S511GeneralDescriptionTheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2PortsPort0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.PortPinAlternateFunctionsP1.5MOSI(usedforIn-SystemProgramming)P1.6MOSO(usedforIn-SystemProgramming)P1.7SCK(usedforIn-SystemProgramming)Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVXDPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVXRI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.PortPinAlternateFunctionsP3.0RXD(serialinputport)P3.1TXD(serialoutputport)P3.2INT0(externalinterrupt0)P3.3INT1(externalinterrupt1)P3.4T0(timer0externalinput)P3.5T1(timer1externalinput)P3.6WR(externaldatamemorywritestrobe)P3.7RD(externaldatamemoryreadstrobe)3SpecialFunctionRegistersAmapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable3-1.Table3-1.AT89S51SFRMapandResetValues0F8H0FFH0F0HB000000000F7H0E8H0EFH0E0HACC000000000E7H0D8H0DFH0D0HPSW000000000D7H0C8H0CFH0C0H0C7H0B8HIPXX0000000BFH0B0HP3111111110B7H0A8HIE0X0000000AFH0A0HP211111111AUXR1XXXXXXX0WDTRSTXXXXXXXX0A7H98HSCON00000000SBUFXXXXXXXX9FH90HP11111111197H88HTCON00000000TMOD00000000TL000000000TL100000000TH000000000TH100000000AUXRXXX00XX8FH80HP011111111SP00000111DP0L00000000DP0H00000000DP1L00000000DP1H00000000PCON0XXX000087HNotethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.InterruptRegisters:TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.Table3-2.AUXR:AuxiliaryRegisterAUXRAddress=8EHResetValue=XXX00XX0bNotBitAddressable–––WDIDLEDISRTO––DISALEBit76543210–ReservedforfutureexpansionDISALEDisable/EnableALEDISALEOperatingMode0ALEisemittedataconstantrateof1/6theoscillatorfrequency1ALEisactiveonlyduringaMOVXorMOVCinstructionDISRTODisable/EnableReset-outDISRTO0ResetpinisdrivenHighafterWDTtimesout1ResetpinisinputonlyWDIDLEDisable/EnableWDTinIDLEmodeWDIDLE0WDTcontinuestocountinIDLEmode1WDThaltscountinginIDLEmodeDualDataPointerRegisters:Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.PowerOffFlag:ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.Table3-3.AUXR1:AuxiliaryRegister1AUXR1Address=A2HResetValue=XXXXXXX0BNotBitAddressable–––––––DPSBit76543210–ReservedforfutureexpansionDPSDataPointerRegisterSelectDPS0SelectsDPTRRegistersDP0L,DP0H1SelectsDPTRRegistersDP1L,DP1H4.InterruptsTheAT89S51hasatotaloffiveinterruptvectors:twoexternalinterrupts(INT0andINT1),twotimerinterrupts(Timers0and1),andtheserialportinterrupt.TheseinterruptsareallshowninFigure6-1.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatTable6-1showsthatbitpositionsIE.6andIE.5areunimplemented.Usersoftwareshouldnotwrite1stothesebitpositions,sincetheymaybeusedinfutureAT89products.TheTimer0andTimer1flags,TF0andTF1,aresetatS5P2ofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.Table6-1InterruptEnable(IE)Register(MSB)(LSB)EA––ESET1EX1ET0EX0EnableBit=1enablestheinterrupt.EnableBit=0disablestheinterruptSymbolPositionFunctionEAIE.7Disablesallinterrupts.IfEA=0,nointerruptisacknowledged.IfEA=1,eachinterruptsourceisindividuallyenabledordisabledbysettingorclearingitsenablebit.–IE.6Reserved–IE.5ReservedESIE.4SerialPortET1IE.3Timer1interruptenablebitEX1IE.2Externalinterrupt1enablebitET0IE.1Timer0interruptenablebitEX0IE.0Externalinterrupt0enablebitUsersoftwareshouldneverwrite1storeservedbits,becausetheymaybeusedinfutureAT89productsAT89S51概述1一般概述該AT89S51是一個(gè)低功耗，高性能CMOS8位微控制器,可在4K字節(jié)的系統(tǒng)編程的閃存存儲(chǔ)器。該設(shè)備是采用Atmel的高密度、非易失性存儲(chǔ)器技術(shù)和符合工業(yè)標(biāo)準(zhǔn)的80C51指令集和引腳。芯片上的Flash程序存儲(chǔ)器在系統(tǒng)中可重新編程或常規(guī)非易失性存編程。通過結(jié)合通用8位中央處理器的系統(tǒng)可編程閃存的單芯片，AT89S51是一個(gè)功能強(qiáng)大的微控制器提供了高度靈活的和具有成本效益的解決辦法，可在許多嵌入式控制中應(yīng)用。在AT89S51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)的Flash閃存，128字節(jié)的RAM，32個(gè)I/O線，看門狗定時(shí)器，兩個(gè)數(shù)據(jù)指針，兩個(gè)16位定時(shí)器/計(jì)數(shù)器，5向量兩級(jí)中斷結(jié)構(gòu)，全雙工串行端口，片上振蕩器和時(shí)鐘電路。此外，AT89S51設(shè)計(jì)了可降至零頻率的靜態(tài)邏輯操作和支持兩種軟件可選的節(jié)電工作模式。在空閑模式下停止CPU的工作，但允許RAM、定時(shí)器/計(jì)數(shù)器、串行接口和中斷系統(tǒng)繼續(xù)運(yùn)行。掉電模式保存RAM中的容，停止振蕩器工作并禁止其它所有部件工作，直到下一個(gè)外部中斷或硬件復(fù)位。2端口P0端口是一個(gè)8位漏極開路雙向I/O端口。作為一個(gè)輸出端口，每個(gè)引腳可驅(qū)動(dòng)8個(gè)TTL輸入。對端口寫“1”P1端口是一個(gè)帶部上拉電阻的8位雙向I/O端口。P1端口的輸出緩沖級(jí)可以驅(qū)動(dòng)四個(gè)TTL輸入。對端口寫“1”，通過部的上拉電阻把端口拉到高電平，此時(shí)可作為輸入口。作為輸入口時(shí)，因?yàn)椴看嬖谏侠娮瑁硞€(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL端口引腳第二功能P1.5MOSI(用于ISP編程)P1.6MISO（用于ISP編程）P1.7SCK(用于ISP編程)P2端口是一個(gè)帶有部上拉電阻的8位雙向I/O端口。P2端口的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL輸入。對端口寫“1”，通過部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。當(dāng)作輸入口使用時(shí)，因?yàn)椴看嬖谏侠娮?，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器P3端口是一組帶有部上拉電阻的8位雙向I/O端口。P3端口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對P3端口寫入“1”時(shí)，他們被部上拉電阻拉高并作為輸入端口。當(dāng)作輸入端時(shí)，被外部拉低的P2端口將用上拉電阻輸出電流（IIL各種特殊功能，如下表所示。端口引腳第二功能P3.0RXD(串行輸入端口)P3.1TXD(串行輸出端口)P3.2INT0(外部中斷0)P3.3INT1（外部中斷1）P3.4T0(定時(shí)/計(jì)數(shù)器0外部輸入）P3.5T1（定時(shí)/計(jì)數(shù)器1外部輸入）P3.6WR（外部數(shù)據(jù)存儲(chǔ)器寫選通）P3.7RD（外部數(shù)據(jù)存儲(chǔ)器讀選通）3特殊功能寄存器特殊功能寄存器（SFR）的片空間分布如表3-1所示。表3-1AT89S51特殊功能寄存器分布圖與復(fù)位值0F8H0FFH0F0HB000000000F7H0E8H0EFH0E0HACC000000000E7H0D8H0DFH0D0HPSW000000000D7H0C8H0CFH0C0H0C7H0B8HIPXX0000000BFH0B0HP3111111110B7H0A8HIE0X0000000AFH0A0HP211111111AUXR1XXXXXXX0WDTRSTXXXXXXXX0A7H98HSCON00000000SBUFXXXXXXXX9FH90HP11111111197H88HTCON00000000TMOD00000000TL000000000TL100000000TH000000000TH100000000AUXRXXX00XX8FH80HP011111111SP00000111DP0L00000000DP0H00000000DP1L00000000DP1H00000000PCON0XXX000087H值得注意的是，這些地址并沒有全部占用，沒有占用的地址也不可使用，讀這些地址將得到一個(gè)隨意的數(shù)值。而寫這些地址單元不能得到預(yù)期的結(jié)果。不要用軟件訪問這些未定義的單元，這些單元是留作以后產(chǎn)品擴(kuò)展用途的，復(fù)位后這些新的位將為0。中斷寄存器：各個(gè)中斷控制位于IE寄存器，5個(gè)中斷源的中斷優(yōu)先級(jí)控制位于IP寄存器。表3-2AUXR輔助寄存器AUXR地址=8EH復(fù)位狀態(tài)=XXX00XX0B不可尋址位–––WDIDLEDISR