本設(shè)計(jì)基于Xilinx公司開發(fā)的FPGA設(shè)電路，將2×4矩陣鍵盤與LED七段數(shù)碼管綜合為一體，通過與8255的連接，作為CPU的I/O端口，可實(shí)現(xiàn)LED燈顯示鍵值行列信息的功能。本設(shè)計(jì)應(yīng)用ISE開發(fā)環(huán)境，通過VHDL硬件描述語言進(jìn)行實(shí)現(xiàn)，并且在ISE中完成本設(shè)計(jì)可通過ISE中原理圖方式與8255及CPU連接，形成完整電路，在進(jìn)行綜合、實(shí)現(xiàn)、時(shí)序仿真，并生成文件后，即可到FPGA，實(shí)現(xiàn)鍵盤在輸入后的穩(wěn)定輸出，并LED目 設(shè)計(jì)任 任務(wù)要 任務(wù)后 設(shè)計(jì)思 程序設(shè) 功能仿 總 設(shè)計(jì)總 參考文 附錄一鍵盤掃描程序及其測試程 附錄二鍵盤消抖程序及其測試程 編程邏輯器件和相應(yīng)的設(shè)計(jì)技術(shù)已經(jīng)成為從事電子系統(tǒng)設(shè)計(jì)的設(shè)計(jì)工程師和科研人員的一項(xiàng)重要設(shè)和能。最佳選擇之一。FPGA二是適用于可編程邏輯器件的硬件編程技術(shù)，即VHDL技術(shù)和Verilog技術(shù)。這兩種硬EDAFPGA/CPLD設(shè)計(jì)任任務(wù)要⑴2×4（其中包含消抖電路LED所使用的器件中，鍵盤為2行4LED數(shù)碼管為2在鍵盤中按下按鍵后，可以在ISE任務(wù)后協(xié)助學(xué)長完成8255模塊和CPU模塊的設(shè)計(jì)（由PicoBlaze軟核實(shí)現(xiàn)，內(nèi)含UART相關(guān)的設(shè)置）,同時(shí)獨(dú)立完成狀態(tài)機(jī)模塊和UART模塊的設(shè)計(jì)，兩種方案結(jié)合在一起，UART，對于我們要獨(dú)立完成的任務(wù)部分在最后會(huì)把各個(gè)模塊連接在一起，在ISE上完（CPUUART），1-1設(shè)計(jì)思鍵盤掃描電I/O2486（2+4）I/OchoosePC5、PC4choose=02-12×4在鍵值未按下時(shí)，PC5、PC4接低電平情況下（對應(yīng)程序中choose=0當(dāng)列線PC3～PC0依次輸出高電平的時(shí)候，輸入PC5和PC4，如果這時(shí)候有按鍵按下，就可以根據(jù)行列電平值“PC3～PC0PC5～PC4）列/PC3～PC0（輸出行/PC5～PC4（輸入012345672-1線不斷循環(huán)的進(jìn)行掃描，同時(shí)鍵盤行線的電平值。掃描電平表如下：10000100001000012-2（choose=0）相應(yīng)的，choose=101111011110111102-3鍵盤消抖電LED七段數(shù)碼管顯示電2-2abcdefg111111000110000111011012111100011011100007111111表-3com012345672-4程序設(shè)鍵盤掃描程（Clock，Kin（ScanSignlnumcanSigalVHDL程序如下：(完整程序代碼在附錄中給出entitykeyvhdlPortClock KIN ScanSignal 輸出列碼(掃描信號num IntegerRange0to 輸出鍵值，8endarchitectureBehavioralofkeyvhdlissignalscans:std_logic_vector(0to5);signalscn:std_logic_vector(0to3);signalcounter:integerrange0to signalstart:bit signalchoose:bit0';--用于選擇PC5、PC4signalcounterb:integerrange0to if ifcounter=3thenendif;if choose=0代表PC5、PC4casecounter when0=>scn<="1000";when1=>scn<="0100";when2=>scn<="0010";whenendcase;end

casecounterwhen0=>scn<="0111";when1=>scn<="1011";when2=>scn<="1101";whenendcase;endif;endiffalling_edge(clock if 8if 次“00ifcounterb=3thenendif;ifcasescans scanswhen"100010"=>num<=0;when"010010"=>num<=1;when"001010"=>num<=2;when"000110"=>num<=3;when"100001"=>num<=4;when"010001"=>num<=5;when"001001"=>num<=6;when"000101"=>num<=7;whenothers=>num<=8;endcase;casescanswhen"011101"=>num<=0;when"101101"=>num<=1;when"110101"=>num<=2;whenwhen"011110"=>num<=4;when"101110"=>num<=5;when"110110"=>num<=6;when"111010"=>num<=7;whenothers=>num<=8;endcase;endif;endif;endend endBehavioral;鍵盤消抖程（Clocknumin（numoutCounternuminCounter若過31個(gè)時(shí)鐘周期，輸入值已發(fā)生改變，則直接重新對輸入進(jìn)行計(jì)數(shù)。msVHDL程序如下：(完整程序代碼在附錄中給出entityxiaodouPort(clock: numin:in integerrange0to8;numout:out integerrange0to8);endarchitectureBehavioralofxiaodousignaltempnum:integerrange0to numsignalcounter:integerrange0to31;signalstart:bit:='0';ifrising_edge(clock)if 8

ifnumin/=tempnumthen---前一輸入與此輸入不同 0ifcounter31 31 endif;endif;endif;endif;endprocess;endBehavioral;LED七段數(shù)碼管顯示程（Clocknuminled2outnuminLEDVHDL程序如下：(完整程序代碼在附錄中給出entityleddisplayPort(clock:innumin:inSTD_LOGIC_VECTOR(0TOled1out:out STD_LOGIC_VECTOR(0TO7);led2out:out endarchitectureBehavioralofleddisplaysignalchoose: ifchoose='0 casenuminwhen " ---最為小數(shù)點(diǎn)when"when"when"when"when"when"when"when"endcasenuminwhen"0000"=>"; "when"when"when"when"when"when"when"when"endcase;endif;endprocess;endBehavioral;功能仿鍵盤掃描電路仿4-1的按鍵400后，num8num0該測試文件是通過ISE自帶的測試激勵(lì)HDLBencher生成，VHDL代碼在附錄中4-2消抖電路仿4-34-4從原理圖中可以看出，numout40～7時(shí)，只用到低位的0。LED數(shù)碼管電路仿4-5numin0～8的數(shù)后，led1outled2out顯示相對應(yīng)的數(shù)值，經(jīng)過真值4-6led同上一小節(jié)的分析，當(dāng)numin的最為1時(shí)，表示無按鍵按下，只有當(dāng)numin為總設(shè)計(jì)總CPU8255控制的程序我們也沒有具體給出。時(shí)序仿真，以及配置等設(shè)計(jì)步驟，到FPGA，在實(shí)際當(dāng)中看到我們的實(shí)驗(yàn)結(jié)果。心得體從知識層面看，我們?nèi)齻€(gè)人從一開始完全不了解硬件描述語言，到現(xiàn)在掌握了VerilogISE、ISE的開發(fā)環(huán)境下，對高效地學(xué)習(xí)，同時(shí)更為迅速的完成老師和學(xué)長分配的任務(wù)。最后，非常感謝老師讓我們有這個(gè)機(jī)會(huì)，去接觸FPGA，并參與到FPGA開發(fā)中去EDA技術(shù)，而不是僅僅拘泥于書本上的講解，這將為我們我們的幫助尤其是學(xué)長為我們實(shí)驗(yàn)準(zhǔn)備了大量相關(guān)的資料并在我們實(shí)驗(yàn)過程中遇到[1]編著《VHDL入門?解惑?經(jīng)典實(shí)例?經(jīng)驗(yàn)總結(jié)》.：航空航天大學(xué)[2]石英，新，編著《ISE應(yīng)用與開發(fā)技巧》.：機(jī)械工業(yè)[3]編著《數(shù)字系統(tǒng)的verilogHDL設(shè)計(jì)》.：機(jī)械工業(yè)[4]編著《VerilogHDL與數(shù)字系統(tǒng)設(shè)計(jì)簡明》：人民郵電附錄一鍵盤掃描程序及其測試程libraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useentitykeyvhdlPort(Clock: KIN:in STD_LOGIC_vector(0to1);ScanSignal:out STD_LOGIC_vector(0to3);num:out IntegerRange0to8endarchitectureBehavioralofkeyvhdlissignalscans:std_logic_vector(0to5);signalscn:std_logic_vector(0to3);signalcounter:integerrange0to3;signalstart:bitsignalchoose:bitsignalcounterb:integerrange0toififcounter=3thenendif;ifchoose='0'thencasecounteriswhen0=>scn<="1000";when1=>scn<="0100";when2=>scn<="0010";when3=>scn<="0001";endcase;end

casecounterwhen0=>scn<="0111";when1=>scn<="1011";when2=>scn<="1101";whenendcase;endif;endprocess;iffalling_edge(clock)thenifstart='0'thenififcounterb=3thenendif;ifchoose='0'thencasescanswhen"100010"=>num<=0;when"010010"=>num<=1;when"001010"=>num<=2;when"000110"=>num<=3;when"100001"=>num<=4;when"010001"=>num<=5;when"001001"=>num<=6;when"000101"=>num<=7;whenothers=>num<=8;endcase;casescanswhen"011101"=>num<=0;when"101101"=>num<=1;when"110101"=>num<=2;whenwhen"011110"=>num<=4;when"101110"=>num<=5;when"110110"=>num<=6;when"111010"=>num<=7;whenothers=>num<=8;endcase;endif;endif;endif;endendprocess; endlibraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_TEXTIO.ALL;USESTD.TEXTIO.ALL;ENTITYkeyvhdltestISENDkeyvhdltest;ARCHITECTUREtestbench_archOFkeyvhdltestISCOMPONENTkeyvhdlPORTClock:InKIN:Instd_logic_vector(0To1);ScanSignal:Outstd_logic_vector(0To3);num:OutINTEGERrange0To8ENDSIGNALClock:std_logic:=SIGNALKIN:std_logic_vector(0To1):=SIGNALScanSignal:std_logic_vector(0To3):="0000";SIGNALnum:INTEGERrange0To8:=0;constantPERIOD:time:=40ns;constantDUTY_CYCLE:real:=0.5;constantOFFSET:time:=0ns;UUT:keyvhdlPORTMAP(Clock=>Clock,KIN=>KIN,ScanSignal=>ScanSignal,num=>num --clockprocessforClockWAITforOFFSET;CLOCK_LOOP:LOOPClock<=WAITFOR(PERIOD-(PERIOD*Clock<=WAITFOR(PERIOD*DUTY_CYCLE);ENDLOOPCLOCK_LOOP;ENDWAITFOR215KIN<=WAITFOR80KIN<=WAITFOR80KIN<=WAITFOR220KIN<=WAITFOR60KIN<=WAITFOR180KIN<=WAITFOR80KIN<=WAITFOR125ENDEND附錄二鍵盤消抖程序及其測試程libraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useentityxiaodouPort(clock: numin:in integerrange0to8;numout:out integerrange0to8);endarchitectureBehavioralofxiaodouissignaltempnum:integerrange0to8;signalcounter:integerrange0to31;signalstart:bit:='0';ifrising_edge(clock)thenifstart='0'thenifnumin/=tempnumthenifcounter=31thenendif;endif;endif;endif;endprocess;endBehavioral;libraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_TEXTIO.ALL;USESTD.TEXTIO.ALL;ENTITYxiaodounext_testISENDxiaodounext_test;ARCHITECTUREtestbench_archOFxiaodounext_testFILERESULTS:TEXTOPENWRITE_MODEISCOMPONENTxiaodouPORT(clock:Innumin:InINTEGERrange0To16;numout:OutINTEGERrange0To16ENDSIGNALclock:std_logic:=SIGNALnumin:INTEGERrange0To16:=0;SIGNALnumout:INTEGERrange0To16:=0;constantPERIOD:time:=10ns;constantDUTY_CYCLE:real:=0.5;constantOFFSET:time:=0ns;UUT:xiaodouPORTMAP(clock=>clock,numin=>numin,numout=>numout --clockprocessforclockWAITforCLOCK_LOOP:clock<=WAITFOR(PERIOD-(PERIOD*clock<=WAITFOR(PERIOD*DUTY_CYCLE);ENDLOOPCLOCK_LOOP;ENDWAITFOR0numin<=1;WAITFOR30ns;numin<=2;WAITFOR330ns;numin<=6;WAITFOR330ns;numin<=1;WAITFOR266ns;ENDEND附錄三LED數(shù)碼管顯示程序及其測試libraryuseIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useentityleddisplayPort(clock:innumin:inSTD_LOGIC_VECTOR(0TOled1out:out STD_LOGIC_VECTOR(0TO7);led2out:out STD_LOGIC_VECTOR(0TO7));endarchitectureBehavioralofleddisplayissignalchoose:bit:='0';ifchoose='0'thencasenuminiswhen ";when"0001"=> ";when"0010"=> ";when"0011"=> ";when"0100"=> ";when"0101"=> ";when"0110"=> ";when"0111"=> ";whenothers=> ";endcase;casenuminwhen ";led2out<=" ";when"0001"=> ";when"0010"=> ";when"0011"=> ";when"0100"=> ";when"0101"=> ";when"0110"=> ";when"0111"=> ";whenoth