#4.頂層仿真測試指令為：dout=32'h0800000b;//jlaterdout=32'h20080042;//earlier:addi$t0,$0,42dout=32'h20090004;//addi$tl,$0,4dout=32'h01095022;//sub$t2,$t0,$tl（操作B一階相關(guān)，操作A二階相關(guān)）dout=32'h01485825;//or$t3,$t2,$t0（操作A一階相關(guān)，操作B三階相關(guān)）dout=32'hac0b000c;//sw$t3,0c($0)dout=32'h8d2c0008;//Iw$t4,08($tl)dout=32'h000c4080;//sll$t0,$t4,2（數(shù)據(jù)冒險）dout=32'h8d2b0008;//Iw$t3,08($tl)dout=32'h012a582b;//situ$t3,$tl,$t2dout=32'h0800000a;//done:jdonedout=32'hl4000001;//later:bne$0,$0,end（分支條件不成立）dout=32'hl000fff4;//beq$0,$0,earlier（分支條件成立）dout=32'h00000000;//end:nopJumpFlag={JR、J、Z}=/top_tb_v/dk.J/top_tb_v/reset/top_tb_w/JumpFlag/t?p_tb_v/Instrudion_idQ-J/tupJb_v/ALU_AQ-J/top_tb_v/ALU_BQ-J/t?p_tb_v/ALUResuItJ/top_tb_v/PC/top_tb_v/uuVMemDout_mbJ^tDp_tb_w/StBll10010OSOOOODa00000000OQOQQQQQ000000000000002c00000OOPStrjqOO國01SI糜碩DOiojtogrooiKaooaooitooooooiio初始指令為J指令,J=l,所以IF_flash=1,清空IF/ID級寄存器，下一周期指令=0.J=l,使PC跳轉(zhuǎn)KJOOOOO04bne分支不成立beq分支成立，Z=1，IF_flash=1，清空IF/ID級寄存器，下一周期指令=0.tooooooilioooooo2l加立即數(shù)4,下一周期操作數(shù)B=4，$0始終寄存0，操作數(shù)A=0，故ALUResult=4數(shù)據(jù)相關(guān)，可以看到前兩個指令的結(jié)果正確轉(zhuǎn)發(fā)到操作數(shù)A與BJftop_tb_v/dk1J/"tnp_tb_v/reset0p-J/'top_tb_?/JumpFlag□io iQ-J/top_tb_v/Instructionjd□800000a |O-Jftop_tb_v/ALU_AODOOOODD .jQ-^JtDp.tb.v/ALU-Boaoooooo jO-】/tsp_tb_v/ALUResult□aoooooo |0000002c IQ-JftDp_tb_v/uutTMemDout_wts□DnoooooJftjap_tb_v/Stall1J?□oo口如0?？诳趞口如0。口口Kooooo0000000laooBoail22llOOQOOO12再］碗而麗1200^0qgg瓦擊6D41)01^85825000蹄i臨dObUDMtoo00.jygaooooDteQ0004Z^SOOOO)L)0口如0口樂to000007e^加立即數(shù)42,下一周期操作數(shù)B=42,$0始終寄存0，操作數(shù)A=0，故ALUResult=42沒有跳轉(zhuǎn)，可以看到PC正常增加LW指令，$t1寄存4,即為操作數(shù)A，

操作數(shù)B為立即數(shù)8Sll位移運算，操作數(shù)為Sa=2同樣的LW指令，下一周期不存在數(shù)據(jù)冒險/top_tb_v/dk，/top_tb_v/resetO-S/top_tb_v/JumpFlagQ-S/tDp_tb_v/lnstructionJdB->>toP_tb_v/ALU_AB-^>toP_tb_v/ALU_BQ-J/tDp_tb_v/ALUResultB-4，t中_出』片/top_tb_v/Liut/MennDoi't_wb4/top_tb_v/Etall100100800000a0000000000000000ooaoctjooJ000002C00000005EtcLfrtoooooo:t8d2b00iIDUaSaZbI00c40ii0mg歷|匚0頃心：1匚 加2fl0D幗)8yq0000042ya000007eyaooooo3e^10000001ifooooooiYjjDOOOOOliaTk}瓦拓

此/痂瓦拓11=)8 1ooooaoiSW指令，操作數(shù)B為立即數(shù)0c。儲存$t3=0000007e,在兩周期后存入DataRAM匹一’Iocici麗iDOIMjoaooiMoooaooinbaoaooiyaooaoo^tooooooJO數(shù)據(jù)冒險，阻塞信號Stall=l,流水線被阻塞SLTU指令，無符號判斷大J指令，向本身跳轉(zhuǎn)，不斷循環(huán)小，A<B?1:0,結(jié)果正確通過頂層仿真分析，證明流水線寄存器與各模塊之間的鏈接正確。至此，流水線MIPS微處理器設(shè)計全部符合要求。七、 綜合約束實現(xiàn)打開PipelineCPU_VGA中的工程文件，將已完成的代碼添加到工程文件中，對工程進(jìn)行綜合、約束、實現(xiàn)，下載到XUPVirtex-HPro開發(fā)實驗板中。接入SVGA顯示器，復(fù)位，每按一下UP鍵，MIPSCPU運行一步。觀察顯示器顯示的結(jié)果，結(jié)果正確。具體操作步驟不再贅述。八、 實驗心得本次實驗代碼編寫部分較為簡單，實驗指導(dǎo)中已經(jīng)很明確的給出了各個模塊中的工作原理與信號之間的邏輯關(guān)系，但由于連接信號眾多，信號名稱相近，很容易由于錄入粗心而產(chǎn)生錯誤，這也是本次實驗最主要的錯誤來源。我認(rèn)為本次實驗的難點在于對流水線CPU多種工作狀態(tài)的整體把握，以及頂層仿真中的糾錯工作。流水線CPU速度更快，多條指令同時運行，這就要求我們對不同指令的運行以及數(shù)據(jù)的傳遞有一定的認(rèn)識。在理論課程中已經(jīng)對流水線CPU有了一定的了解學(xué)習(xí)，通過實驗可以更直觀更透徹的學(xué)習(xí)其具體流程和實現(xiàn)方式。 由于各子模塊的結(jié)構(gòu)清晰、原理明確，仿真中出現(xiàn)的錯誤也很容易糾正，但在頂層模塊中存在各級數(shù)據(jù)轉(zhuǎn)發(fā)，同一指令各級運行時間不同，錯誤的排查有一定困難。實驗中我出現(xiàn)的錯誤也主要在頂層仿真中。出現(xiàn)錯誤時我一般會先觀察錯誤波形所對應(yīng)的輸入波形是否正確，若正確再順著輸入信號向前一級排查直至信號源。如果輸入信號全部正常，則問題在于錯誤波形所在模塊，仔細(xì)檢查模塊的各個輸入輸出信號之間的邏輯關(guān)系是否正確，再具體排查一遍代碼中是否存在問題，基本就可以發(fā)現(xiàn)錯誤所在。我在頂層仿真時EX級與MEM級的輸出信號存在紅線，將其展開發(fā)現(xiàn)信號部分錯誤，檢查輸入信號也是同樣問題。繼續(xù)向前一級檢查發(fā)現(xiàn)ID/EX寄存器與EX/MEM寄存器的輸出信號位數(shù)不對，查看頂層設(shè)計代碼發(fā)現(xiàn)編寫寄存器時個別D觸發(fā)器的輸入輸出信號位數(shù)沒有定義，改正后頂層仿真就正確了。在ISE工程文件中同樣要注意信號參數(shù)的傳遞，工程中時鐘信號有一定變化，模塊連接過程中也要注意傳遞信號的名稱是否與工程定義的一致?；仡櫿麄€實驗過程，最重要的是嚴(yán)謹(jǐn)細(xì)致的態(tài)度。筆誤這種錯誤最容易避免，也最容易發(fā)生，排查起來卻相當(dāng)費力。只要再細(xì)心一點，實驗就能更輕松一點。對于仿真軟件的應(yīng)用也更為熟練，學(xué)習(xí)到很多新的方便的小功能，對于分析波形很有幫助。實驗中的不足之處在于對ISE軟件的應(yīng)用還是很生澀，很多功能仍未學(xué)習(xí)到，一些錯誤提示也不理解，還需要進(jìn)一步學(xué)習(xí)。附錄一：流水線MIPS微處理器的原理框圖時一啪口啞性如日UTSU占3<宙姉弭後u皿&M§IBAUO』mauiy-p/^H^ysis^p<e軍E耕Q總W潴房￡展^popn^IVhe一日。瑁mvXa-V3jsmvAmie.iuojSS-xa還核宀XVP田嚎嘗帶5專蕓亳應(yīng)皂口擊Joypo-gFW—waauHEas放初｝ssa.ippwd.iiJrLf44§faiUlUqprlppa總-I卷—君祈擊W—君；wuawW*亳&SS2F-Fvlplw』m欄iwutcolHHM￡m<PIT!..!:<彳電官日M.II—緒由一!堂1專囪巴od附錄二：部分代碼Decode中ALUCode狀態(tài)機reg[4:0]ALUCode;always@(*)beginif(op==R_type_op)begincase(funct)ADD_funct:ALUCode<=alu_add;ADDU_funct:ALUCode<=alu_add;AND_funct:ALUCode<=alu_and;XOR_funct:ALUCode<=alu_xor;OR_funct:ALUCode<=alu_or;NOR_funct:ALUCode<=alu_nor;SUB_funct:ALUCode<=alu_sub;SUBU_funct:ALUCode<=alu_sub;SLT_funct:ALUCode<=alu_slt;SLTU_funct:ALUCode<=alu_sltu;SLL_funct:ALUCode<=alu_sll;SLLV_funct:ALUCode<=alu_sll;SRL_funct:ALUCode<=alu_srl;SRLV_funct:ALUCode<=alu_srl;SRA_funct:ALUCode<=alu_sra;default:ALUCode<=alu_sra;endcaseendelsebegincase(op)BEQ_op:ALUCode<=alu_beq;BNE_op:ALUCode<=alu_bne;BGEZ_op:beginendendendendBGEZ_op:beginendendendendBGTZ_op:beginif(rt==BGTZ_rt)ALUCode<=alu_bgtz;BLEZ_op:beginif(rt==BLEZ_rt)ALUCode<=alu_blez;BLTZ_op:beginif(rt==BLTZ_rt)ALUCode<=alu_bltz;ADDI_op:ALUCode<=alu_add;ADDIU_op:ALUCode<=alu_add;ANDI_op:ALUCode<=alu_andi;XORI_op:ALUCode<=alu_xori;ORI_op:ALUCode<=alu_ori;SLTI_op:ALUCode<=alu_slt;SLTIU_op:ALUCode<=alu_sltu;SW_op:ALUCode<=alu_add;LW_op:ALUCode<=alu_add;default:ALUCode<=alu_add;endcaseendendALUmoduleALU(Result,ALUCode,A,B);input[4:0]ALUCode; //Operationselectinput[31:0] A,B;output[31:0] Result;reg[31:0]Result;//Shiftoperation:">>>"willperformanarithmeticshift,buttheoperand//mustberegsignedregsigned[31:0]B_reg;always@(B)begin B_reg=B;end//DecodedALUoperationselect(ALUsel)signals〃略//ALUResultdatapathwire[31:0]sum,B1;wireBinvert;assignBinvert=~(ALUCode==alu_add);assignB1=BA(32(Binvert}};adder_32bitsadd(.a(A),.b(B1),.ci(Binvert),.s(sum),.co());always@(*)begincase(ALUCode)alu_add:Result<=sum;alu_and:Result<=A&B;alu_xor:Result<=AAB;alu_or:Result<=AIB;alu_nor:Result<=~(AIB);alu_sub:Result<=sum;alu_andi:Result<=A&(16'd0,B[15:0]};alu_xori:Result<=AA{16'd0,B[15:0]};alu_ori:Result<=AI{16'd0,B[15:0]};alu_sll:Result<=B<<A;alu_srl:Result<=B>>A;alu_sra:Result<=B_reg>>>A;

alu_slt:Result<=(A[31]&&(~B[31]))ll((A[31]A~B[31])&&sum[31]);alu_sltu:Result<=((?A[31])&&B[31])ll((A[31]?AB[31])&&sum[31]);alu_jr:Result<=A;default:Result<=32'b0;endcaseendendmodule頂層模塊PC,moduleMipsPipelineCPU(clk,reset,JumpFlag,Instruction_id,ALU_A,ALU_B,ALUResult,PC,RegWriteData_wb,Stall);inputclk;inputreset;output[2:0]JumpFlag;output[31:0]Instruction_id;output[31:0]ALU_A;output[31:0]ALU_B;output[31:0]ALUResult;output[31:0]PC;output[31:0]RegWriteData_wb;outputStall;//IFmodulewire[31:0]Instruction_id;wirePC_IFWrite,J,JR,Z,IF_flush;wire[31:0]JumpAddr,JrAddr,BranchAddr,NextPC_if,Instruction_if;assignJumpFlag={JR,J,Z};assignIF_flush=ZllJllJR;IFIF(//input.clk(clk),.reset(reset),.Z(Z),.J(J),.JR(JR),,PC_IFWrite(PC_IFWrite),.JumpAddr(JumpAddr),,JrAddr(JrAddr),.BranchAddr(BranchAddr),//output.Instruction_if(Instruction_if),.PC(PC),.NextPC_if(NextPC_if));//IF->IDRegisterwire[31:0]NextPC_id;dffre#(32)dffre1(.d(Instruction_if),.en(PC_IFWrite),.r(IF_flushlreset),.clk(clk),.q(Instruction_id));dffre#(32)dffre2(.d(NextPC_if),.en(PC_IFWrite),.r(IF_flush|reset),.clk(clk),.q(NextPC_id));//IDModulewire[4:0]RtAddr_id,RdAddr_id,RsAddr_id;wireRegWrite_wb,MemRead_ex,MemtoReg_id,RegWrite_id,MemWrite_id;wireMemRead_id,ALUSrcA_id,ALUSrcB_id,RegDst_id,Stall;wire[4:0]RegWriteAddr_wb,RegWriteAddr_ex,ALUCode_id;wire[31:0]RegWriteData_wb,Imm_id,Sa_id,RsData_id,RtData_id;IDID(.clk(clk),.Instruction_id(Instruction_id),.NextPC_id(NextPC_id),.RegWrite_wb(RegWrite_wb),.RegWriteAddr_wb(RegWriteAddr_wb),.RegWriteData_wb(RegWriteData_wb),.MemRead_ex(MemRead_ex),.RegWriteAddr_ex(RegWriteAddr_ex),.MemtoReg_id(MemtoReg_id),.RegWrite_id(RegWrite_id),.MemWrite_id(MemWrite_id),.MemRead_id(MemRead_id),.ALUCode_id(ALUCode_id),.ALUSrcA_id(ALUSrcA_id),.ALUSrcB_id(ALUSrcB_id),.RegDst_id(RegDst_id),.Stall(Stall),.Z(Z),.J(J),.JR(JR),.PC_IFWrite(PC_IFWrite),.BranchAddr(BranchAddr),.JumpAddr(JumpAddr),.JrAddr(JrAddr),.Imm_id(Imm_id),.Sa_id(Sa_id),.RsData_id(RsData_id),.RtData_id(RtData_id),.RtAddr_id(RtAddr_id),.RdAddr_id(RdAddr_id),.RsAddr_id(RsAddr_id));//ID->EXRegisterwireMemtoReg_ex,RegWrite_ex,ALUSrcA_ex,ALUSrcB_ex,RegDst_ex;wire[4:0]ALUCode_ex,RdAddr_ex,RsAddr_ex,RtAddr_ex;wire[31:0]Sa_ex,Imm_ex,RsData_ex,RtData_ex;dffr#(2)WB_I_E(.d({MemtoReg_id,RegWrite_id}),.r(Stall|reset),.clk(clk),.q({MemtoReg_ex,RegWrite_ex}));dffr#(2)M_I_E(.d({MemWrite_id,MemRead_id}),.r(Stalllreset),.clk(clk),.q({MemWrite_ex,MemRead_ex}));dffr#(8)EX_I_E(.d({ALUCode_id,ALUSrcA_id,ALUSrcB_id,RegDst_id}),.r(Stall|reset),.clk(clk),.q({ALUCode_ex,ALUSrcA_ex,ALUSrcB_ex,RegDst_ex}));dffr#(32)Data_Sa(.d(Sa_id),.r(Stall|reset),.clk(clk),.q(Sa_ex));dffr#(32)Data_Imm(.d(Imm_id),.r(Stall|reset),.clk(clk),.q(Imm_ex));dffr#(32)Data_Rs(.d(RsData_id),.r(Stall|reset),.clk(clk),.q(RsData_ex));dffr#(32)Data_Rt(.d(RtData_id),.r(Stall|reset),.clk(clk),.q(RtData_ex));dffr#(15)Data_I_E(.d({RdAddr_id,RsAddr_id,RtAddr_id}),.r(Stall|reset),.clk(clk),.q({RdAddr_ex,RsAddr_ex,RtAddr_ex}));//EXModulewire[31:0]ALUResult_mem,ALUResult_ex,MemWriteData_ex;wire[4:0]RegWriteAddr_mem;wireRegWrite_mem;EXEX(.RegDst_ex(RegDst_ex),.ALUCode_ex(ALUCode_ex),.ALUSrcA_ex(ALUSrcA_ex),.ALUSrcB_ex(ALUSrcB_ex),.Imm_ex(Imm_ex),.Sa_ex(Sa_ex),.RsAddr_ex(RsAddr_ex),.RtAddr_ex(RtAddr_ex),.RdAddr_ex(RdAddr_ex),.RsData_ex(RsData_ex),.RtData_ex(RtData_ex),.RegWriteData_wb(RegWriteData_wb),.ALUResult_mem(ALUResult_mem),.RegWriteAddr_wb(RegWriteAddr_wb),.RegWriteAddr_mem(RegWriteAddr_mem),.RegWrite_wb(RegWrite_wb),.RegWrite_mem(RegWrite_mem),.RegWriteAddr_ex(RegWriteAddr_ex),.ALUResult_ex(ALUResult_ex),.MemWriteData_ex(MemWriteData_ex),.ALU_A(ALU_A),.ALU_B(ALU_B));assignALUResult=ALUResult_ex;〃EX->MEMwireMemtoR