PAGEPAGE1 西華大學(xué)實(shí)驗(yàn)報(bào)告第組.第組實(shí)驗(yàn)報(bào)告（計(jì)算機(jī)類）開(kāi)課學(xué)院及實(shí)驗(yàn)室：實(shí)驗(yàn)時(shí)間：年月日學(xué)生姓名學(xué)號(hào)成績(jī)學(xué)生所在學(xué)院年級(jí)/專業(yè)/班課程名稱EDA技術(shù)（機(jī)械）課程代碼實(shí)驗(yàn)項(xiàng)目名稱十三進(jìn)制計(jì)數(shù)器（狀態(tài)機(jī)方法）項(xiàng)目代碼指導(dǎo)教師項(xiàng)目學(xué)分一、實(shí)驗(yàn)?zāi)康?.了解VHDL語(yǔ)言編程方法，學(xué)會(huì)熟練運(yùn)用quartus軟件2.了解如何使用狀態(tài)機(jī)方法設(shè)計(jì)十三進(jìn)制計(jì)數(shù)器二、內(nèi)容與設(shè)計(jì)思想1.用狀態(tài)機(jī)給出的狀態(tài)轉(zhuǎn)換圖S0S4S3S2S1/0/0 /0/0S0S4S3S2S1/0/0S12S5S12S5/0 /0S11S6 S11S6S8S10S9S7/0 /0S8S10S9S7/0 /0/0 2.十三進(jìn)制計(jì)數(shù)器引腳圖三、使用環(huán)境winXP或win7、quartusii編程環(huán)境四、核心代碼及調(diào)試過(guò)程狀態(tài)機(jī)方法設(shè)計(jì)十三進(jìn)制計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityh31is port(cp:instd_logic;clocksignal q:outstd_logic_vector(3downto0);stateoutput op:outstd_logiccarryoutput );endh31;architecturert1ofh31istypestateis(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);stateasenumerationsignalpresentstate:state;signalnextstate:state;signalqn:std_logic_vector(3downto0); begin swichtonextstate:Process(cp) begin ifcp'eventandcp='1'then presentstate<=nextstate; endif; endprocessswichtonextstate; changestatemode:process(presentstate) begin casepresentstateis whens0=>nextstate<=s1; qn<="0001"; op<='0'; whens1=>nextstate<=s2; qn<="0010"; op<='0'; whens2=>nextstate<=s3; qn<="0011"; op<='0'; whens3=>nextstate<=s4; qn<="0100"; op<='0'; whens4=>nextstate<=s5; qn<="0101"; op<='0'; whens5=>nextstate<=s6; qn<="0110"; op<='0'; whens6=>nextstate<=s7; qn<="0111"; op<='0'; whens7=>nextstate<=s8; qn<="1000"; op<='0'; whens8=>nextstate<=s9; qn<="1001"; op<='0'; whens9=>nextstate<=s10; qn<="1010"; op<='0'; whens10=>nextstate<=s11; qn<="1011"; op<='0'; whens11=>nextstate<=s12; qn<="1100"; op<='0'; whens12=