1、smt pcb/panel layout,smt team 2015-03-22,pcb design guideline,revision record,purpose,based on the requirements of production process , in the layout and circuit board design process , there is a standard to follow , to achieve high efficiency in the production of assembly , easy assembly, low cost,

2、 and high quality target. the content is only applicable to the related database, some are for reference only .,content,pcb layout rules text marking for silkscreen layer pcb fiducial mark design pcb fixed position hole smt component pad design pth component pad design through-hole(via)design trace

3、design other limitation,pcb layout rules,v-cut layout rule : chips to v-cut line should be more than 1mm, otherwise will damage chips or will change to use stamp cut design , will add the pcb cost the distance to pcb edge 0.5mm, can not layout the trace, the distance to pcb edge 1.0mm,can not layout

4、 the any component the distance to pcb edge 5mm, can not layout the components height over 25mm, otherwise cuter will damage components,pcb layout rules,v-cut layout rules : pcb trace to v-cut should be more then s=0.5mm safety buffer, otherwise will have the risk to damage the trace. when we use v-

5、cut pcb thickness 1.0mm to 3mm(1.0mm to 0.5mm + smt pallet) pcb outline is square type or rectangle type, irregular shape can not use the v-cut,irregular shape,pcb layout rules,stamp design : stamp design only for irregular pcb, pcb to pcb layout distance is 2mm, v-cut only 0.3mm stamp design parame

6、ters,pcb layout rules,v-cut vs stamp layout : pcs to pcs distance only 0.3mm for v-cut, we can save the pcb layout cost stamp cut design, pcb pcs to pcs distance is 2mm base on same pcs design with different cut type( stamp/v cut), the pcb cost will impact 10- 25% v-cut pcb will be cut by machine, b

7、ut stamp cut will broken by op and have stress then damage the components,v-cut machine,pcb/panel layout,why dont choose single pcb for smt process : we need to put the each single pcb on carrier when do smt process but carrier cave and single pcb have tolerance , so always happen solder paste print

8、ing misalignment then will get the shift/tombstone process issue sometimes will happen single pcb lift up from smt carrier and will have the chips mounting shift/missing process issues,put the single pcb on the carrier,pcb/panel layout,factors of impact pcb cost pcb layout fine pitch components pane

9、l v-cut/stamp cut/pcb conveyor edge size pcb drill hole size/quantity pcb material cost pcb process easy/complicated , process spec pcb surface finished process also impact cost, osp/ims/eing/imt pcb outline, regular shape is cheaper than irregular shape ,text marking for silk layer,the current situ

10、ation: we received the gerber file for uk design team ,no silk layer be found we can not directly confirm polarity of component on the pcb , can not confirm the location of component ,easily to confirm ic shift or not . in the production adjustment x, y coordinate and confirmation the location compl

11、etely rely on engineering drawings ,big waste of time.,no silk layers in the gerber file,no text mark on the pcb,text marking for silk layer,as the icon text marking design we can accept . we can quickly inspection location where there are problems.,silkscreen,text marking,text marking for silk laye

12、r,component outline ph= 0.40.5 acceptable ; ph 320 .,other limitation,pip parts limit all of the through hole part must be designed in second to avoid the use of hand soldering process the first surface is necessary to use the smd type part or through hole parts pin and parts body can not outstand p

13、cb second surface the spec of pin out of pcb surface in pip process : pin length pcb thickness + 0.30.6 mm the insert parts in pcb can not tilt, dumping or easy to loose state.,other limitation,other limitation,choose the component :the use of chip components in the smt stage as far as possible, red

14、uce the waste of human action.,pth parts to smd,pth parts to smd,pth parts to smd,pth parts to smd,other limitation,no trace cutting or jump wires process on mass production models.,pcb pad size should be match with the size of components , if the same parts have different appearance size ,the layou

15、t or according to process proposals to special layout, must conform the rule。all of pad design need to non-solder mask design. passive component pad size the general rlc component： place outline area do not overlap,do not overlap,other limitation,for component higher than 5mm, need to keep same dist

16、ance/clearance on pcb surface free from component to avoid shadow effect and causing aoi limiation.,d = h,other limitation,gerber file layers requirement,smd layer: component pad , reference this layer to design stencil aperture,gerber file layers requirement,silk layer: smd component text marking include body outline , pin assignment ,component name ,polari