1、第3章 原理圖輸入設(shè)計方法Quartus II 版操作 課程講義,下一章,本章內(nèi)容,何時使用 原理圖設(shè)計輸入 常用文件介紹 設(shè)計步驟 元件庫 和 Altera 宏的使用 如何將VHDL代碼文件生成 圖形 符號,何時使用 原理圖設(shè)計輸入 ？,符合 傳統(tǒng)的 電路設(shè)計 習(xí)慣 一般只是在 “top-level”(頂層)文件中使用？,Quartus II常用文件介紹,一般步驟,電路的模塊劃分 設(shè)計輸入 器件和引腳指配 編譯與排錯 功能仿真和時序仿真 編程與配置，設(shè)計代碼的芯片運(yùn)行,電路的模塊劃分,人工 根據(jù)電路功能 進(jìn)行 模塊劃分 合理的模塊劃分 關(guān)系到 電路的性能 實現(xiàn)的難易程度 根據(jù)模塊劃分和系統(tǒng)功

2、能 確定： PLD芯片型號 模塊劃分后，就可以進(jìn)行 具體設(shè)計 了,設(shè)計輸入,一般EDA軟件允許3種設(shè)計輸入： HDL語言 電路圖 波形輸入,圖形設(shè)計輸入的過程,+,+,圖形設(shè)計:圖元,圖形設(shè)計:端口,如何編寫一個新的圖形文件？,FILE-NEW出現(xiàn)以下對話窗，選擇如下：,如何調(diào)入元件？,Edit-Insert Symbol 出現(xiàn)下面窗口,將 自己編寫的 符號調(diào)入,從 標(biāo)準(zhǔn)庫中 調(diào)入,將符號之間連線,調(diào)入I/O端口元件符號,2類 標(biāo)準(zhǔn)庫,Megafunctions/LPM 宏模塊 功能復(fù)雜、參數(shù)可設(shè)置的模塊 Primitives 基本圖元 簡單的、功能固定的邏輯元件，不可調(diào)整參數(shù),如何將VHDL

3、設(shè)計編程Symbol,VHDL文件編譯后，自動生成同名的符號文件 符號文件的擴(kuò)展名稱（*.bsf） 調(diào)入過程如下：,何為 ？ 器件和引腳指配,器件指配 為設(shè)計輸入 選擇合適的PLD器件型號 何謂引腳指配 將設(shè)計代碼（圖形）中的端口（PORT） 和 PLD芯片的引腳 （PIN） 對應(yīng)起來的. 指配文件 MAX+PLUS II： “ *.acf ” Quartus II： “ *.qsf ”,器件和引腳指配的方法,方法有2種 在軟件的菜單界面中指配 修改指配文件（是文本文件）,菜單界面中 指 配,修改指配文件,CHIP io_2d_lock BEGIN |iVD :INPUT_PIN = 7; |

4、iHD :INPUT_PIN = 8; |iDENA :INPUT_PIN = 6; |iCLK :INPUT_PIN = 211; |oCLK :OUTPUT_PIN = 237; |oVD :OUTPUT_PIN = 234; |oHD :OUTPUT_PIN = 233; |oDENA :OUTPUT_PIN = 235; . DEVICE = EPF10K30AQC240-2; END; .,編譯與排錯,編譯過程有2種，作用分別為： 語法編譯：只是綜合并輸出網(wǎng)表 編譯設(shè)計文件，綜合產(chǎn)生門級代碼 編譯器只運(yùn)行到綜合這步就停止了 編譯器只產(chǎn)生估算的延時數(shù)值 完全的編譯：包括編譯，網(wǎng)表輸出，

5、綜合，配置器件 編譯器除了完成以上的步驟，還要將設(shè)計配置到ALTERA的器件中去 編譯器根據(jù)器件特性產(chǎn)生真正的延時時間和給器件的配置文件,功能仿真和時序仿真,仿真的概念： 在設(shè)計代碼下載到芯片前，在EDA軟件中對設(shè)計的輸出進(jìn)行波形仿真。 常用的2種仿真模式 功能仿真 對設(shè)計的邏輯功能進(jìn)行仿真 時序仿真 對設(shè)計的邏輯功能和信號的時間延時進(jìn)行仿真。 仿真前還要做的工作 輸入信號的建立,Quartus II軟件中 關(guān)于仿真的原文,2種 仿真文件,矢量波形文件： a Vector Waveform File (.vwf) 文本矢量文件 a text-based Vector File (.vec),編

6、程與配置,最后， 如果仿真 也正確 的話， 那我們就可以 將設(shè)計代碼 配置或者編程 到 芯片 中了 編程的文件類型 對于CPLD或者EPC2，ECS1等配置芯片，編程文件擴(kuò)展名為：“ *.POF “ 配置的文件類型 對于FPGA芯片，配置文件擴(kuò)展名為：“ *.SOF “,硬件設(shè)計和軟件設(shè)計的時間協(xié)調(diào),軟件模塊劃分，器件的初步信號確定（主要是根據(jù)需要的I/O引腳的數(shù)量） 軟件設(shè)計，硬件外圍電路設(shè)計和器件選擇 軟件仿真 仿真完成后，器件信號的重新審核，進(jìn)行硬件電路圖設(shè)計 綜合調(diào)試 完成,設(shè)計的幾個問題,如何組織多個設(shè)計文件的系統(tǒng)？，項目的概念。 時鐘系統(tǒng)如何設(shè)計？ 電路的設(shè)計功耗 高速信號的軟件和

7、硬件設(shè)計,The end.,以下內(nèi)容為正文的引用，可不閱讀。,常用EDA工具軟件,EDA軟件方面，大體可以分為兩類： PLD器件廠商提供的EDA工具。較著名的如： Altera公司的Max+plusII和QuartusII、 Xilinx公司的FoundationSeries、 Latice-Vantis公司的ispEXERTSystem。 第三方專業(yè)軟件公司提供的EDA工具。常用的有： Synopsys公司的FPGACompilerII、 ExemplarLogic公司的LeonardoSpectrum、 Synplicity公司的Synplify。 第三方工具軟件是對CPLD/FPGA生產(chǎn)

8、廠家開發(fā)軟件的補(bǔ)充和優(yōu)化，如通常認(rèn)為Max+plusII和QuartusII對VHDL/VerilogHDL邏輯綜合能力不強(qiáng)，如果采用專用的HDL工具進(jìn)行邏輯綜合，會有效地提高綜合質(zhì)量。,ALTERA 公司的EDA合作伙伴,硬件描述語言：起源,是電子電路的文本描述。 最早的發(fā)明者：美國國防部，VHDL,1983 大浪淘沙，為大者二： VHDL 和 Verilog HDL 其他的小兄弟： ABEL、AHDL、System Verilog、System C。,一個D觸發(fā)器的VHDL代碼例子,- VHDL code position: p83_ex4_11_DFF1 - - LIBARY IEEE;

9、 - USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT (CLK:INBIT; D:INBIT; Q:OUTBIT ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND (CLK=1) AND ( CLKLAST_VALUE = 0) THEN - 嚴(yán)格的CLK信號上升沿定義 Q = D; END IF; END PROCESS; END ARCHITECTURE bhv;,代碼實體（510）,代碼結(jié)構(gòu)體（1120）,如何使

10、用VHDL來設(shè)計電路？,VHDL設(shè)計電路的的5步曲 語言編碼 邏輯綜合 功能和時序仿真 器件適配 器件編程,使用MAX+PLUS II軟件的設(shè)計過程,MAX+PLUS II設(shè)計過程說明,Compiler Netlist Extractor（編譯器網(wǎng)表提取器）: 通過該過程生成設(shè)計項目的網(wǎng)表文件, Database Builder(數(shù)據(jù)庫構(gòu)建器 ): 用于將所有的設(shè)計文件集成到項目數(shù)據(jù)庫中 如果指定端口的實體已被抽取. 則從盤中讀取. cnf文件信息就可以了, 因而節(jié)省了時間. Logic Synthesizer (邏輯綜合器): 選擇合適的邏輯化簡算法, 去除冗余和無用邏輯, 有效使用器件的邏

11、輯資源. Fitter(適配器) 將電路適配到某個PLD器件中。 Timing SNF Extractor(時序SNF文件提取器) 產(chǎn)生用于時序仿真的網(wǎng)表文件 Assembler（匯編器） 產(chǎn)生用于器件編程的目標(biāo)代碼,其他的HDL綜合工具,Altera公司 MAX+PLUS II 10.2（已經(jīng)停止發(fā)行，新器件不支持） QUARTUS II 5.0（推薦使用） Xilinx 公司 ISE 7.0：Xilinx公司集成開發(fā)的工具 Foundation: Xilinx公司早期開發(fā)工具，逐步被ISE取代 ISE Webpack： Webpack是xilinx提供的免費(fèi)開發(fā)軟件，功能比ISE少一些，可

12、以從xilinx網(wǎng)站下載,有了HDL語言后？,硬件設(shè)計人員 的工作過程 已經(jīng) 類似與 軟件設(shè)計人員，那么 這種模式的好處是？ 讓我們先看看原來是如何做的,Compiler Netlist Extractor（編譯器網(wǎng)表提取器）,The Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename(s) of the CNF(s) are based on the project na

13、me. Example The Compiler Netlist Extractor also creates a single HIF that documents the hierarchical connections between design files. This module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that translate ADFs and SMFs for use with MAX+PLUS I

14、I. During netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together. 返回,Database Builder(數(shù)據(jù)庫構(gòu)建器 ):,The Compiler module that builds a single, fully flattened project database that integrates all th

15、e design files in a project hierarchy. The Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the original hierarchi

16、cal project. The database thus preserves the electrical connectivity of the project. The Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains on

17、ly the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. As it creates the database, the Database Builder examines the logical completeness and consistency of the project, and checks for boundary

18、 connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing. 返回,Logic Synthesizer,The Compiler module that synthesizes the logic in a projects design files. Using the database created by

19、 the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. For projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the

20、 project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly. The Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented

21、 with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used. 返回,Fi

22、tter（適配器）,The Compiler module that fits the logic of a project into one or more devices. Using the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the best logic cell

23、location and selects appropriate interconnection paths and pin assignments. The Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or terminate compilation

24、. The Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project compiles successfully, the Fit File is overwritten. You can back-annotate the assignments in the fi

25、le to preserve them in future compilations. 返回,Timing SNF Extractor(時序SNF文件提取器),The Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis. The Timing SNF Extractor is turned on with the Timing SNF E

26、xtractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF E

27、xtractor. A timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including del

28、ay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project. 返回,Assembler（匯編器）,The Compiler module that creates one or mo

29、re programming files for programming or configuring the device(s) for a project. The Assembler module completes project processing by converting the Fitters device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam

30、 Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A pr

31、ojects. If you turn on the Enable JTAG Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After compilation

32、, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu). The programming files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several o

33、ther programming hardware manufacturers also provide programming support for Altera devices. 返回,Simulation Mode,Functional Simulates the behavior of flattened netlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can a

34、lso provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of logic level changes, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (the ratio of outp

35、ut ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). Timing Uses a fully compiled netlist that includes estimated or actual timing information. You can use Tcl commands and scripts to control simulation and to provide vec

36、tor stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec). This type of simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling between 1 and 0 dur

37、ing simulation, compared to the total number of output ports present in the netlist). Timing using Fast Timing Model Performs a timing simulation using the Fast Timing Model to simulate fastest possible timing conditions with the fastest device speed grade,Megafunctions/LPM,Arithmetic Components Gat

38、es I/O Components Memory Compiler Parallel Flash Loader Megafunction SignalTap II Logic Analyzer Megafunction Storage Components,Arithmetic Components,altaccumulate divide* altfp_add_sub lpm_abs altfp_mult lpm_add_sub altmemmult lpm_compare altmult_accum lpm_counter altmult_add lpm_divide altsqrt lpm_mult altsquare parallel_add,Gates,busmuxlpm_inv lpm_andlpm_mux lpm_bustri lpm_or lpm_clshift lpm_xor lpm_constant mux lpm_decode,I/O Components,altcdr_rxaltdqs altcdr_tx altgxb altclkctrl altlvds_r