1、CHAPTER 10 Memory Interface(存儲(chǔ)器接口)(P. 332),目的（P. 332）,譯碼存儲(chǔ)器地址，并利用譯碼器的輸出選擇不同的存儲(chǔ)器器件。 確定存儲(chǔ)器的地址范圍。 解釋如何將RAM和ROM與微處理器接口。,10-1 MEMORY DEVICES(存儲(chǔ)器件)(P. 332),Memory Pin Connections(存儲(chǔ)器引腳)(P. 333),FIGURE 10-1 A pseudo-memory component illustrating the address, data and control connections,10.1存儲(chǔ)器件（P. 332）,基于

2、微處理器的計(jì)算機(jī)系統(tǒng)的內(nèi)存包括以下兩種存儲(chǔ)器： 只讀存儲(chǔ)器（ROM），永久性地存儲(chǔ)駐留在系統(tǒng)中的程序和數(shù)據(jù)，即使未接電源，其存儲(chǔ)內(nèi)容也不會(huì)改變，也被稱為非易失性存儲(chǔ)器。 ROM在計(jì)算機(jī)外被編程，且一般只能讀出數(shù)據(jù)。存放系統(tǒng)軟件和永久性系統(tǒng)數(shù)據(jù)。分為掩膜ROM、可編程只讀存儲(chǔ)器（PROM）、可擦除可編程只讀存儲(chǔ)器（EPROM）、快閃存儲(chǔ)器（EEPROM）四種。 隨機(jī)存取存儲(chǔ)器（RAM），即讀/寫存儲(chǔ)器，也被稱為易失性存儲(chǔ)器，在接通電源后正常操作下能夠被重復(fù)讀出、寫入數(shù)據(jù)，但在沒有電源的情況下它們不會(huì)保留數(shù)據(jù)。存放臨時(shí)數(shù)據(jù)和應(yīng)用軟件。主要有靜態(tài)RAM（SRAM）、動(dòng)態(tài)RAM（DRAM）兩種。,存儲(chǔ)

3、器引腳,地址線 所有存儲(chǔ)器件都有地址輸入，用來選擇存儲(chǔ)器件中的一個(gè)存儲(chǔ)單元。一個(gè)存儲(chǔ)器件的地址線個(gè)數(shù)由其中的存儲(chǔ)單元的數(shù)目決定；反之，存儲(chǔ)單元的數(shù)目可由地址線的數(shù)目來推斷。例如，1K個(gè)存儲(chǔ)單元的存儲(chǔ)器件有10個(gè)地址線（A0-A9），如果一個(gè)存儲(chǔ)器件有11個(gè)地址線，則它有2048（2K）個(gè)內(nèi)部存儲(chǔ)單元。,數(shù)據(jù)線 通過數(shù)據(jù)線向存儲(chǔ)器件輸入數(shù)據(jù)以便存儲(chǔ)，或從存儲(chǔ)器件提取數(shù)據(jù)以便讀出。例如，一個(gè)存儲(chǔ)器件有8個(gè)I/O線（D0-D7），這意味著這個(gè)存儲(chǔ)器件在它的每個(gè)存儲(chǔ)單元中存儲(chǔ)8位數(shù)據(jù)，這樣的一個(gè)8位寬的存儲(chǔ)器件常常被稱為字節(jié)寬存儲(chǔ)器。 存儲(chǔ)器件的目錄表通常用存儲(chǔ)單元數(shù)乘以每單元的位數(shù)表示存儲(chǔ)器件的規(guī)格

4、，例如，一個(gè)存儲(chǔ)器件有1K存儲(chǔ)單元，每單元存儲(chǔ)8位數(shù)據(jù)，則制造商經(jīng)常把它的規(guī)格寫為1K X 8。,選擇線 每個(gè)存儲(chǔ)器件都有一個(gè)或幾個(gè)輸入信號(hào)用來選擇或允許存儲(chǔ)器件。這種輸入信號(hào)常稱為片選（CS）、片允許（CE）或選擇（S）輸入。 如果CE、CS或S輸入有效（為邏輯0），則存儲(chǔ)器件執(zhí)行一次讀或?qū)懖僮鳌Ｈ绻菬o效的（為邏輯1），則存儲(chǔ)器件不能進(jìn)行讀或?qū)懖僮鳌Ｈ舸嬖诓恢挂粋€(gè)選擇線，則所有這些選擇線都必須被激活，才可以讀或?qū)憯?shù)據(jù)。,控制線 ROM通常只有一個(gè)控制輸入，而RAM通常有一個(gè)或兩個(gè)控制輸入。 ROM上的控制輸入通常是輸出允許（OE）或是輸出選通（G），它允許數(shù)據(jù)從ROM的輸出數(shù)據(jù)線上流出。

5、若OE和選擇輸入CS均有效，則輸出被允許；若OE無效，則輸出被禁止。 RAM存儲(chǔ)器件有一個(gè)或兩個(gè)控制輸入。若只有一個(gè)控制輸入，它常被稱為R/W。只有器件被選擇輸入（CS）選中時(shí)，該控制線選擇一次讀操作或?qū)懖僮鳌Ｈ鬜AM有兩個(gè)控制輸入，通常被標(biāo)為WE（或W）和OE（或G）。這里，WE（寫允許）必須有效，才能執(zhí)行一次存儲(chǔ)器寫操作，OE必須有效，才能執(zhí)行一次存儲(chǔ)器讀操作。當(dāng)這兩個(gè)控制信號(hào)線（WE和OE）都存在時(shí)，它們不能同時(shí)有效；若兩個(gè)控制輸入均無效（邏輯1），則數(shù)據(jù)既不寫入也不讀出，數(shù)據(jù)線處于高阻抗?fàn)顟B(tài)。,例1,例2,38線譯碼器（74LS138）,10.2.4 雙24線譯碼器（74LS139）,

6、Memory Reference(存儲(chǔ)器接口),To interface memory to the microprocessor, there are generally four problems to be solved. Address Connections Data Connections Selection Connections Control Connections,Address Connections(地址線連接)(P. 344),The address connections include chip inner address connections and chip

7、 selection address connections. Chip inner address connections Connect the address connections of a memory chip with the microprocessor correspondingly. For example, the 2716 EPROM has 11 address ant the 8086/8088 microprocessor has 20. So address connections A10-A0 of 8086/8088 are connected to add

8、ress inputs A10-A0 of the EPROM.,Chip selection address connections When the 8086/8088 microprocessor is compared to the 2716 EPROM, a difference in the number of address connections is apparent-the EPROM has 11 address connections and the microprocessor has 20. There is a mismatch that must be corr

9、ected. If only 11 of the 8086/8088s address pins are connected to the memory, the 8086/8088 will see only 2K bytes of memory instead of the 1M bytes that it “expects” the memory to contain. The decoder corrects the mismatch by decoding the address pins that do not connect to the memory component. Th

10、e decoders outputs are connected to the chip selection or enable inputs of the memory.,Simple NAND Gate Decoder(簡單的與非門譯碼器)(P. 344),EXAMPLE 10-1,A19,A18,A17,A16,A15,A14,A13,A12,A11,8088 數(shù)據(jù) 總線,A0,A10,O0,O7,CE,OE,FIGURE 10-13 A simple NAND gate decoder,2716,8088 地址 總線,D0-D7,0,Chip selection address con

11、nections,Chip inner address connections,Memory starting address,Memory ending address,Here, the 2K EPROM is decoded at memory address locations FF800H-FFFFFH.,The 3-to-8 Line Decoder (74LS138)(3-8線譯碼器)(P. 346),EXAMPLE 10-2,A0,A12,O0,O7,2764,OE,CE,CE,CE,CE,CE,CE,CE,CE,A,B,C,G2A,G2B,G1,A13,A14,A15,A16

12、,A17,A18,A19,D0-D7,0,0,0,1,2,3,4,5,6,7,1#,2#,3#,4#,5#,6#,7#,8#,138,8088 Address Bus,8088 Data Bus,Chip selection address connections,Chip inner address connections,Memory starting address,Memory ending address,Here, the 1# 2764 EPROM is decoded at memory address locations F0000H-F1FFFH.,The 2# 2764

13、EPROM is decoded at memory address locations F2000H-F3FFFH. The 3# 2764 EPROM is decoded at memory address locations F4000H-F5FFFH. The 4# 2764 EPROM is decoded at memory address locations F6000H-F7FFFH. The 5# 2764 EPROM is decoded at memory address locations F8000H-F9FFFH. The 6# 2764 EPROM is dec

14、oded at memory address locations FA000H-FBFFFH. The 7# 2764 EPROM is decoded at memory address locations FC000H-FDFFFH. The 8# 2764 EPROM is decoded at memory address locations FE000H-FFFFFH.,10-3 8088 MEMORY INTERFACE(8088和存儲(chǔ)器接口)(P. 352),FIGURE 10-20,A0,A11,O0,O7,2732,OE,CE,CE,CE,CE,CE,CE,CE,CE,A,B

15、,C,G2A,G2B,G1,A12,A13,A14,A16,A17,A18,A19,8088 Address Bus,8088 Data Bus,0,1,2,3,4,5,6,7,1#,2#,3#,4#,5#,6#,7#,8#,A15,IO/M,+5V,138,WAIT,1K,F8000H-F8FFFH,F9000H-F9FFFH,FA000H-FAFFFH,FB000H-FBFFFH,FC000H-FCFFFH,FD000H-FDFFFH,FE000H-FEFFFH,FF000H-FFFFFH,164,QA,QB,QC,QD,QE,QF,QG,QH,CLK,CLR,CLK,CLK,1Tw,RD

16、Y1,AEN1,RDY2,WAIT,READY,8284A 時(shí)鐘 產(chǎn)生器,8086 或 8088,READY,SI,1,FIGURE 9-17 A circuit that will cause between 0 and 7 wait states,QA,QB,QC,RDY1,CLK,T1,T2,T3,Tw,T4,10-4 8086 MEMORY INTERFACE(8086存儲(chǔ)器接口)(P. 360),The 8086 microprocessor differ from the 8088 in three ways: The data bus is 16 bits wide instea

17、d of 8 bits wide as on the 8088. The IO/M pin of the 8088 is replaced with an M/IO pin. There is a new control signal called bus high enable.,The 16-bit data bus must be divided into two separate sections (banks) that are eight bits wide so that the microprocessor can write to either half (8-bit) or

18、 both halves (16-bit). One bank (low bank) holds all the even-numbered memory locations, and the other bank (high bank) holds all the odd-numbered memory locations. The data written to or read from the low bank are transferred through A0-A7, and the data written to or read from the high bank are tra

19、nsferred through A8-A15.,FIGURE 10-27 The high (odd) and low (even) 8-bit memory bans of the 8086 microprocessor,A0,TABLE 10-3 Memory bank selection using BHE and A0,Bank selection is accomplished in two ways： Separate decoders are used for each bank. A separate write signal is developed to select a

20、 write to each bank of the memory.,A0,1#,2#,FIGURE 10-28,High bank,Low bank,Specify the address range of the memory with an example of 1# and 2# memories.,Memory starting address,Memory ending address,Here, the 1# and 2# memory components are decoded at memory address locations 00000H-1FFFFH.,A 16-b

21、it memory decoder that places memory at locations 60000H-6FFFFH.,FIGURE 10-30,Example Interface 8088 microprocessor to Intel 2114 (1K*4) and Intel 2716 (2K*8) memory components to design a memory system composed of 1KB RAM and 4KB ROM. Plot the interface circuit and write down the address ranges of every memory component.,A0-A9,1# 2114,WE,CS,D0-D3,OE,CE,OE,62256,A0-A10,D0-D7,D0-D7,A0-A10,2#,D4-D7,CE,3#,4#,A,B,C,G2A,G2B,G1,A11,A12,A13,A15,A16,A17,A18,0,1,2,3,4,5,6,7,A14,IO/M,+5V,138,WAIT,1K