1、1Mixed Verilog/VHDL simulation with NC-SimMixed Verilog/VHDL simulation with NC-Sim義隆電子義隆電子王偉民王偉民29 29 Aug 2001Aug 20012AgendaAgendaOverview of Cadence NC-SimOverview of Cadence NC-SimSimulating Multi-Language SourceSimulating Multi-Language SourceMixed VHDL testbench/Verilog Gate Level SimulationMi

2、xed VHDL testbench/Verilog Gate Level SimulationSummary Summary 3Overview of Cadence NC-Sim Overview of Cadence NC-Sim Coverage TrackingSingle Kernel EngineCentral ElaborationVerilogCompilationVHDLCompilationOMIVHPIVPIPLI& ToolsEngines，Model，ExternalIndustryStandardInterfacesAdvancedDebugEnviron

3、mentSignalscanNclaunchSimVisionVerilogTiming VHDLComplete simulation environment targeted at SoC design- High-performance mixed-languages simulation solution- Increased simulation productivity through advanced debug tools- Low-overhead integrated code coverage4NC-Sim: The heart of a complete simulat

4、ion solutionNC-Sim: The heart of a complete simulation solutionDigital SimulationNC-SimAlgorithm DesignTransistor LevelC/C+ TestbenchAnalog/Mixed-SignalStatic HDL AnalysisCode CoverageAnalysisSimulation DebugTransaction AnalysisLinks to physicalDesign verificationSupport for mixedAnalog/Digital Desi

5、gnsSystem-level DesignsAnd TestbenchTransaction-basedTestbench design5Interleaved Native Compiled CodeInterleaved Native Compiled Code Present and future extensions to Native Compiled Code address the performance challenges of a single-simulation strategy Multiple representations behavioral / RTL /

6、gate / UDP Multiple paradigms Event / Cycle Multiple languages Verilog / HDL Mixed signal Analog / Digital6How Native Compiled Code is interleavedHow Native Compiled Code is interleavedElaborate, Generate CodeUpdateKKKKKKVerilogVHDLSimulation - XVHDLCompileASTSimulator-XCompileVerilogCompileVSTTime

7、update codeEvent schedulingKernel (distributed)7Simulating Multi-Language SourceSimulating Multi-Language SourceCo-execution of Verilog and VHDL simulation modelsCo-execution of Verilog and VHDL simulation modelsThe foreign model import shellThe foreign model import shellImporting a VHDL model into

8、a Verilog designImporting a VHDL model into a Verilog designImporting a Verilog model into a VHDL designImporting a Verilog model into a VHDL design8Co-executing Verilog and VHDLCo-executing Verilog and VHDLCo-execution is the simultaneous simulation of multiple simulation languages in a single proc

9、ess. Co-execution is a more efficient solution than co-simulation, which requires multiple simulation processes to communicate over an IPC backbone. 9Co-executing Verilog and VHDLCo-executing Verilog and VHDLYou can import VHDL into a Verilog model or Verilog into a VHDL model - Compile Verilog with

10、 ncverilogncverilog or ncvlogncvlog and VHDL with ncvhdl ncvhdl You encapsulate second-language hierarchies in a model shell - You can use the ncshellncshell utility to automatically create the shellEach imported hierarchy retains its own features and limitations - Case sensitivity - PLI vs. CIF 10U

11、nderstanding the Model ShellUnderstanding the Model ShellThe model shell encapsulates the foreign model. It converts port types and generics( parameters) . It defines the foreign entity, and its type, and for non- INCA simulators,defines the slave simulator.Example Shell to Import VHDL into VerilogE

12、xample Shell to Import VHDL into Verilog module inv ( o , i ) ( * const integer foreign = “ VHDL ( event ) WORKLIB.inv:proc”; * ); output o ; input i ; endmodule11Understanding the Model ShellUnderstanding the Model ShellExample Shell to Import Verilog into VHDLExample Shell to Import Verilog into V

13、HDL Library ieee; use ieee.std_logic_1164.all; entity inv is port ( o : out std_logic; i : in std_logic); end inv; architecture verilog of inv is attribute foreign of verilog: architecture is “ VERILOG (event ) worklib.inv:module”; begin end;12Generating a Model Shell with ncshellGenerating a Model

14、Shell with ncshellUse ncshellncshell to generate a shell for foreign model importSyntax :Syntax : ncshell -import vhdl -into verilog ncshell -import vhdl -into verilog -options library.entity:architecture -options library.entity:architecture ncshell -import verilog -into vhdl ncshell -import verilog

15、 -into vhdl -options library.cell:view -options library.cell:view13Generating a Model Shell with ncshellGenerating a Model Shell with ncshellExampleExample ncshell -import vhdl -into verilog inv:procncshell -import vhdl -into verilog inv:proc Produces shell file inv.vsinv.vs and compiles into view s

16、hell ncshell -import verilog -into vhdl invncshell -import verilog -into vhdl inv Produces shell file inv.vhdinv.vhd and analyzes it into architecture verilog Produces package file inv_comp.vhdinv_comp.vhd containing component definition You can also use ncshellncshell to generate shells to import L

17、MSFI, FMI, or Swift models into a VHDL design.14Importing VHDL Source Code into NC VerilogImporting VHDL Source Code into NC Verilog Define libraries and the work library in cds.libcds.lib and hdl.varhdl.var include $CDS_INST_DIR/tools/inca/files/cds.lib include $CDS_INST_DIR/tools/inca/files/cds.li

18、b include $CDS_INST_DIR/tools/inca/files/hdl.var include $CDS_INST_DIR/tools/inca/files/hdl.var Analyze the VHDL source files with ncvhdlncvhdl ncvhdl and2.vhdncvhdl and2.vhd Generate and compile a Verilog shell with ncshellncshell ncshell -import vhdl -into verilog and2:procncshell -import vhdl -in

19、to verilog and2:proc15Importing VHDL Source Code into NC VerilogImporting VHDL Source Code into NC Verilog Compile the Verilog source files with ncvlogncvlog ncvlog test.v top.v ncvlog test.v top.v Elaborate and simulate the design with ncelab ncelab and ncsimncsim ncelab top:modulencelab top:module

20、 ncsim top:modulencsim top:module16Importing Verilog Source Code into NC VHDLImporting Verilog Source Code into NC VHDL Define libraries and the work library in cds.libcds.lib and hdl.varhdl.var include $CDS_INST_DIR/tools/inca/files/cds include $CDS_INST_DIR/tools/inca/files/cds.lib.lib include $CD

21、S_INST_DIR/tools/inca/files/hdl.var include $CDS_INST_DIR/tools/inca/files/hdl.var Compile the Verilog source files with ncvlogncvlog ncvlog and2.vncvlog and2.v Generate and analyze a VHDL shell with ncshellncshell ncshell -import verilog -into vhdlncshell -import verilog -into vhdl and2:module and2

22、:module17Importing Verilog Source Code into NC VHDLImporting Verilog Source Code into NC VHDL Analyze VHDL source, package, and configuration files with ncvhdlncvhdl ncvhdl test.vhd top.vhd ncvhdl test.vhd top.vhd Elaborate and simulate the design with ncelab ncelab and ncsimncsim ncelab top: struct

23、ncelab top: struct ncsim top: structncsim top: struct18Mixed VHDL testbench/Mixed VHDL testbench/ Verilog Verilog Gate Level Simulation Gate Level SimulationMixed VHDL/Verilog designs Mixed VHDL/Verilog designs Verilog sign-off gate level simulationVerilog sign-off gate level simulationMixed VHDL te

24、stbench/Verilog GateMixed VHDL testbench/Verilog Gate Level Simulation examples Level Simulation examples19Mixed VHDL/Verilog designs Mixed VHDL/Verilog designs Testbench(Block,IP,Whole Chip) :VHDL,VerilogRTL designs(Block,IP):VHDL,VerilogGate Level designs(Block,IP):VHDL,VerilogWhole Chip gate leve

25、l designs:VerilogVerilog Designs Simulation:NC-Verilog,Verilog-XLVHDL Designs Simulation:NC-VHDLMixed VHDL/Verilog Designs :NC-SimDebug Environments:NCLaunch,Simvision,Signalscan20Verilog sign-off gate level simulation Verilog sign-off gate level simulation Why Verilog sign-off gate level, not VHDL

26、?Standard cell library (Verilog,VHDL model)EDA design flow requirements ASIC Vendor sign-off requirementsGate level simulation performancePre-layout and Post-layout SDF backannotation21Mixed VHDL testbench/Verilog GateMixed VHDL testbench/Verilog Gate Level Simulation Examples Level Simulation Examp

27、les RTL Level :VHDL testbench,VHDL designGate Level : VHDL testbench,Synthesized Verilog design Standard cell library: Compile Verilog library into NC- Verilog Library Pre-Layout SDF from Synopsys and PrimetimePost-Layout SDF from RC Extraction & Primetime22hdl.var and cds.lib setuphdl.var and c

28、ds.lib setuphdl.varhdl.varinclude $CDS_INST_DIR/tools/inca/files/hdl.vardefine VIEW_MAP ( $VIEW_MAP, .v = v)define WORK worklibcds.libcds.libinclude $CDS_INST_DIR/tools/inca/files/cds.libdefine worklib ./worklibdefine ncvlog_lib asiclib/ncvlog_libassign ncvlog_lib TMP ./tmp_vlib23Compile , Elaborate

29、Compile , Elaboratencvlog design.vncvlog design.vncshell -messages -into vhdl -import verilog ncshell -messages -into vhdl -import verilog worklib worklib.design:v.design:v produce design.vhd,design_comp.vhdncvhdl design_comp.vhd design.vhd testbench.vhd ncvhdl design_comp.vhd design.vhd testbench.v

30、hd top.vhd top.vhdncsdfc design.sdfncsdfc design.sdfncelab -access +rwc -messages -libverbose -ncelab -access +rwc -messages -libverbose -sdf_cmd_file sdf_cmd_file sdf.cmd -sdf sdf.cmd -sdf_verbose worklib.top_entity:top_architecture_verbose worklib.top_entity:top_architecture 24SimulateSimulate & Debug & Debugncsim -tcl -input setup.tcl -gui ncsim -tcl -input setup.tcl -gui worklib worklib.top_entity:top_architecture.top_entity:top_architectureInvoke Simvision and Signalscan to debug simulation resultsVHDL/Veri