1、實驗五 AD轉(zhuǎn)換電路的設(shè)計與實現(xiàn)（4課時）實驗?zāi)康?.學(xué)習(xí)AD0809模數(shù)轉(zhuǎn)換芯片的工作原理和接口電路時序特征。2.學(xué)習(xí)點陣顯示器的工作原理和驅(qū)動方法。3.掌握利用VHDL語言設(shè)計并行總線時序的方法。4.掌握AD芯片通道切換方法和點陣顯示器靈活驅(qū)動的設(shè)計方法。實驗原理1. ADC0809接口電路圖2. ADC0809芯片工作時序圖：位置輸入和控制線共4條，ALE為位置鎖存允許輸入線，高電平有效，當(dāng)ALE線為高電平時，位置鎖存與譯碼器將A，B，C三條位置線的位置信號進行鎖存，經(jīng)譯碼后被選中的通道的模擬量進轉(zhuǎn)換器進行轉(zhuǎn)換，A，B，C為位置輸入線，用于選通IN0-IN7的一路模擬量輸入，通道選擇表如

2、下表所示：CBA選擇的通道000IN0001IN1010IN2111IN7數(shù)字量輸出及控制線：11條 START為轉(zhuǎn)換啟動信號，當(dāng)START上升沿時，所有內(nèi)部寄存器清零；下跳沿時，開始進行A/D轉(zhuǎn)換；在轉(zhuǎn)換期間，START應(yīng)保持低電平。EOC為轉(zhuǎn)換結(jié)束信號，當(dāng)EOC為高電平時，表明轉(zhuǎn)換結(jié)束；否則，表明正在進行A/D轉(zhuǎn)換。D7-D0為數(shù)字量輸出總線。要注意：實驗箱電路板上的D0-D7的標(biāo)注是反的。即D7應(yīng)該是最低位，D0應(yīng)該是最高位。REF(-)接GND，REF(+)接VCC5V。3. 電路改進及相應(yīng)的簡化時序ADC0809接口的完全控制時序比較復(fù)雜，通過增加三個與門后（實驗箱上的實際電路，見上

3、圖）可以簡化接口時序。電路改進后的時序：CSWRINTRDDATACLOCKS0S1S2S3S34.依據(jù)時序圖歸納時序狀態(tài)狀態(tài)S0：CS=1，WR=1，RD=0（請求轉(zhuǎn)換）狀態(tài)S1：CS=0，WR=0，RD=0（此時0809進行轉(zhuǎn)換，若轉(zhuǎn)換結(jié)束，將INT置1）狀態(tài)S2：CS=1，WR=0，RD=1（讀數(shù)據(jù)總線值）狀態(tài)S3：CS=0，WR=0，RD=0（空閑，等待下一次轉(zhuǎn)換啟動）5.16*16點陣顯示器件 列選信號為SEL0-SEL3經(jīng)4-16譯碼器后，最右端為第一列；行選信號為L0-L16，最上方為第一行。點陣顯示接口對應(yīng)關(guān)系表：Sel3Sel2Sel1Sel0點亮列號1111第1列1110第

4、2列1101第3列.0000第16列實驗內(nèi)容與要求1. 設(shè)計一個AD0809模數(shù)轉(zhuǎn)換芯片的驅(qū)動電路，能將A0通道的模擬電壓(0-5V)值以16位光柱對應(yīng)顯示，即電壓低時光柱矮，電壓高時光柱高。此光柱建議采用點陣顯示器的一列（16個LED）。（6）2. 在上述設(shè)計的基礎(chǔ)上，擴展顯示精度。即采用點陣顯示器的256個LED表示5V之內(nèi)的電壓大?。娣e表示法）。（3）3. 改進電路，使之能測量并分別顯示AD0809芯片至少4個通道的電壓值。建議采用4個光柱（16級）顯示（3分）。相應(yīng)程序：Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_log

5、ic_unsigned.all;use ieee.std_logic_arith.all;Entity zjf1 isPort (clk,int:in std_logic; data:in std_logic_vector(7 downto 0); CS,WR,RD:out std_logic; DX: out std_logic_vector(15 downto 0); End entity zjf1;Architecture ADC0809 of zjf1 isType state is(st0,st1,st2,st3,st4,st5,st6);Signal current_state,

6、next_state: state:=st0;Signal zj:std_logic_vector(7 downto 0);Signal q:std_logic_vector(3 downto 0);Signal lock:std_logic;BeginProcess(clk)Begin if(clk'event and clk='1')then current_state<=next_state; End if;End process;Process(current_state,int)isBegin Case current_state is when st0

7、 =>CS<='0'WR<='0'RD<='0'lock<='0'next_state<=st1;-chu shi tai when st1 =>CS<='1'WR<='1'RD<='0'lock<='0'next_state<=st2;-qing qiu zhuan huan -when st2 =>CS<='0'WR<='0'RD<=&#

8、39;0'lock<='0' -if(int='0') then next_state<=st3; -else next_state<=st2;-dengdaikaishi - end if; when st2 =>CS<='0'WR<='0'RD<='0' if(int='1') then next_state<=st3; else next_state<=st2;-dengdaijieshu end if; when st3 =>

9、;CS<='1'WR<='0'RD<='1'lock<='0'next_state<=st4; when st4 =>CS<='1'WR<='0'RD<='1'lock<='1'next_state<=st0;-kai qi shu ju suo cun lock -when st6 =>CS<='0'WR<='0'RD<='0'l

10、ock<='1'next_state<=st0; when others=>next_state<=st0; end case;End process;Process (lock) beginif lock='1' and lock'event then zj<=data; end if;end process;q<=zj(7 downto 4);process(q) begin case q is WHEN"0000"=>DX<="0000000000000000"

11、WHEN"0001"=>DX<="0000000000000001"WHEN"0010"=>DX<="0000000000000011"WHEN"0011"=>DX<="0000000000000111"WHEN"0100"=>DX<="0000000000001111"WHEN"0101"=>DX<="0000000000011111"

12、WHEN"0110"=>DX<="0000000000111111"WHEN"0111"=>DX<="0000000001111111"WHEN"1000"=>DX<="0000000011111111"WHEN"1001"=>DX<="0000000111111111" WHEN"1010"=>DX<="0000011111111111"

13、;WHEN"1011"=>DX<="0000111111111111"WHEN"1100"=>DX<="0001111111111111"WHEN"1101"=>DX<="0011111111111111"WHEN"1110"=>DX<="0111111111111111"WHEN"1111"=>DX<="1111111111111111"

14、;WHEN OTHERS=>NULL; END CASE; END PROCESS;End ADC0809;2.library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;Entity zjf2 isPort (clk,int:in std_logic; data:in std_logic_vector(7 downto 0); CS,WR,RD:out std_logic; WX: out std_logic_vector(3 downto 0

15、); DX: out std_logic_vector(15 downto 0); End entity zjf2;Architecture ADC0809 of zjf2 isType state is(st0,st1,st2,st3,st4,st5,st6);Signal current_state, next_state: state:=st0;Signal zj:std_logic_vector(7 downto 0);Signal QH:std_logic_vector(3 downto 0);Signal QL:std_logic_vector(3 downto 0);Signal

16、 shu2:std_logic_vector(3 downto 0);Signal lock:std_logic;Signal shu1:std_logic_vector(3 downto 0);BeginProcess(clk)Begin if(clk'event and clk='1')then current_state<=next_state; shu1<=shu1-1;End if;End process;Process(current_state,int)isBegin Case current_state is when st0 =>CS

17、<='0'WR<='0'RD<='0'lock<='0'next_state<=st1;-chu shi tai when st1 =>CS<='1'WR<='1'RD<='0'lock<='0'next_state<=st2;-qing qiu zhuan huan when st2 =>CS<='0'WR<='0'RD<='0'

18、lock<='0' if(int='0') then next_state<=st3; else next_state<=st2;-dengdaikaishi end if; when st3 =>CS<='0'WR<='0'RD<='0' if(int='1') then next_state<=st4; else next_state<=st3;-dengdaijieshu end if; when st4 =>CS<='

19、1'WR<='0'RD<='1'lock<='0'next_state<=st5; when st5 =>CS<='1'WR<='0'RD<='1'lock<='1'next_state<=st6;-kai qi shu ju suo cun lock when st6 =>CS<='0'WR<='0'RD<='0'lock<='1

20、'next_state<=st0; when others=>next_state<=st0; end case;End process;Process (lock) beginif (lock='1' and lock'event) then zj<=data; end if; WX<=shu1; end process;QH<=zj(7 downto 4);QL<=zj(3 downto 0);process(QH)beginEnd process;process(QH,QL) begin if(shu1<QH

21、) then shu2<="1111" elsif shu1=QH THEN shu2<=QL ; else shu2<="0000" END IF;END PROCESS; PROCESS(CLK) BEGIN case shu2 is WHEN"0000"=>DX<="0000000000000000"WHEN"0001"=>DX<="1000000000000000"WHEN"0010"=>DX<

22、="1100000000000000"WHEN"0011"=>DX<="1110000000000000"WHEN"0100"=>DX<="1111000000000000"WHEN"0101"=>DX<="1111100000000000"WHEN"0110"=>DX<="1111110000000000"WHEN"0111"=>DX<

23、="1111111000000000"WHEN"1000"=>DX<="1111111100000000"WHEN"1001"=>DX<="1111111110000000" WHEN"1010"=>DX<="1111111111000000"WHEN"1011"=>DX<="1111111111100000"WHEN"1100"=>DX<

24、;="1111111111110000"WHEN"1101"=>DX<="1111111111111000"WHEN"1110"=>DX<="1111111111111100"WHEN"1111"=>DX<="1111111111111111"WHEN OTHERS=>NULL; END CASE; END PROCESS;End ADC0809;3.Library ieee;Use ieee.std_logic_

25、1164.all;Use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;Entity zjf3 isPort (clk,int:in std_logic; data:in std_logic_vector(7 downto 0); CS,WR,RD:out std_logic; DZ: out std_logic_vector(2 downto 0); DX: out std_logic_vector(15 downto 0); WX: out std_logic_vector(3 downto 0); End entity

26、zjf3;Architecture ADC0809 of zjf3 isType state is(st0,st1,st2,st3,st4,st5,st6);Signal current_state, next_state: state:=st0;Signal zj0,zj1,zj2,zj3:std_logic_vector(7 downto 0);Signal q:std_logic_vector(3 downto 0);Signal shu1: integer range 0 to 3;Signal shu2: integer range 0 to 3; Signal lock:std_l

27、ogic;BeginProcess(clk)Begin if(clk'event and clk='1')then current_state<=next_state; End if;End process;Process(current_state,int)isBegin Case current_state is when st0 =>CS<='0'WR<='0'RD<='0'lock<='0'next_state<=st1;-chu shi tai when

28、st1 =>CS<='1'WR<='1'RD<='0'lock<='0'next_state<=st2;-qing qiu zhuan huan when st2 =>CS<='0'WR<='0'RD<='0'lock<='0' if(int='0') then next_state<=st3; else next_state<=st2;-dengdaikaishi end

29、if; when st3 =>CS<='0'WR<='0'RD<='0' if(int='1') then next_state<=st4; else next_state<=st3;-dengdaijieshu end if; when st4 =>CS<='1'WR<='0'RD<='1'lock<='0'next_state<=st5; when st5 =>CS<='1

30、'WR<='0'RD<='1'lock<='1'next_state<=st6;-kai qi shu ju suo cun lock when st6 =>CS<='0'WR<='0'RD<='0'lock<='1'next_state<=st0; when others=>next_state<=st0; end case;End process;Process (lock) beginif lock

31、='1' and lock'event then if shu2>3 then shu2<=0; else shu2<=shu2+1; end if; case shu2 isWHEN 0 =>DZ<="000"zj0<=data;WHEN 1 =>DZ<="001"zj1<=data;WHEN 2 =>DZ<="010"zj2<=data;WHEN 3 =>DZ<="011"zj3<=data; En

32、d case; End if; End process;-Process (lock) -begin-if lock='1' and lock'event then -zj<=data; -end if;-end process;-q<=zj(7 downto 4);Process (clk) is Beginif rising_edge(clk) then if shu1>3 then shu1<=0; else shu1<=shu1+1; end if; case shu1 isWHEN 0 =>q<=zj0(7 downto 4);WX<="0000"WHEN 1 =>q<=zj1(7 downto 4);WX<="0001"WHEN 2 =>q<=zj2(7 downto 4);WX<="0010"WHEN 3 =>q<=zj3(7 downto 4);WX<="0011" End case; End if; End process