1、第七講Dracula LVSLPE & Postsim分層設(shè)計(jì)(shj)李福樂 第一頁(yè)，共74頁(yè)。Outline LVS的常用設(shè)置與錯(cuò)誤類型 LPE/PRE版圖寄生提取 后仿真 分層設(shè)計(jì)(shj)的幾個(gè)問題第二頁(yè)，共74頁(yè)。LVS Internal FlowRead databaseTop cell nameExpand dataFrom topExtract deviceand parametersFilter unuseddeviseReduce deviceas specifiedBuilt map of correspondenceTrace frompadsBuild DeviceA

2、nd node mapsComparisonand Output第三頁(yè)，共74頁(yè)。Filter unused devise*descriptionsystem= gds2filter-lay-opt= BCDEHJKORfilter-sch-opt= BCDEHJKOR在lvs command file中的設(shè)定(sh dn)語(yǔ)句B gate is floating, not connect to any pad through a source/drainC gate connect to power or ground and either the source or drain is fl

3、oatD gate is floating, S/D nets have only a POWER path and no paths to any padE gate is floating, S/D nets have only a GND path and no paths to any padF MOSN devices that have the gate tied to a GROUNDG MOSP devices that have the gate tied to a POWERH with both the source and drain nets tied to the

4、POWER第四頁(yè)，共74頁(yè)。Filter unused devise*descriptionsystem= gds2filter-lay-opt = BCDEHJKORfilter-sch-opt= BCDEHJKOR在lvs command file中的設(shè)定(sh dn)語(yǔ)句I with both the source and drain nets tied to the GROUNDJ gate tied to either POWER or GND and source and drain tied togetherK with source and drain having no pa

5、ths to any padL either source or drain is floatingR resistors and diods with at least one floating terminalU both the source and drain are floatingZ floating bipolar transistors,diods,and resistors第五頁(yè)，共74頁(yè)。LVS Initial Node PairsLVS comparison using text extracted from the schematic and layout as a s

6、tarting point LVS result heavily rely on the matching of input labels Use CPOINT-FILE command (in *Description block) to specify the label matching of layout and schematic*DescriptionCPOINT-FILE = INITNAME.TXT In INITNAME.TXT : Layout name Schematic name in vin gnd vss 現(xiàn)在用的lvs文件中沒有這個(gè)(zh ge)command，要

7、用的自己填加第六頁(yè)，共74頁(yè)。LVS Check Option; lvs checkslvschkxre lpercent=0 wpercent=0 resval=1 capval=1 在lvs command file中的設(shè)定(sh dn)A smashes series capacitaorsC froms CMOS gates such as INVERTORs,NORs,NANDs,AOIs,and OAIsE uses size infomation to match MOS,BJT and resistor parallel devicesF filters the unused

8、MOS devices,for example,gate arraysG filters both the schematic and the layout in the same wayK keeps paralle devices unsmashedL same as the C option expect does not form AOI and OAI gatesO forms paralles and series MOS stuructures even if neither is connected to power or groundP checks the ELEMENT

9、capacitors polarity第七頁(yè)，共74頁(yè)。LVS Check Option; lvs checkslvschkxre lpercent=0 wpercent=0 resval=1 capval=1 在lvs command file中的設(shè)定(sh dn)R smashes series resistorsS smashes MOS split-gates that are formed as SUPI or SDWI devices to a single SUP or SDW device,respectivelyU reports in the descrepancy fil

10、e(.LVS) only the unmatched schematic and unmatched layout devices on matched nodes (type 4,5,and 6 LVS errors)X carryes out the comparison at the taransistor level (that is,no swap allowed) X dont use with S or L option.Z randomly matches devices with a common matches terminal and other terminals fl

11、oating,and filters out devices with path to any text pads所以在task1:layout的電阻(dinz)合并成1個(gè)了第八頁(yè)，共74頁(yè)。LVS Device Reduction Dracula is capable of performing LVS up to gate levelGate information is extracted from layout by device reduction Gate information is extracted stage-by-stagePrimitive structures by

12、device extraction include: MOS, BJT, Res, Dio and Cap第九頁(yè)，共74頁(yè)。LVS Device ReductionSecond Level Structure PUP Out, IN1, IN2, SUP Out, IN1, IN2, 第十頁(yè)，共74頁(yè)。LVS Device ReductionSecond Level Structure PDW Out, IN1, IN2, SDW Out, IN1, IN2, 第十一頁(yè)，共74頁(yè)。LVS Device ReductionGate Level Structure PUPI out1,IN1,IN

13、2 SUP Out,IN3,out1AOI Out, IN1, IN2, IN3SDWI out2,IN1,IN2 PDW Out,IN3,out2第十二頁(yè)，共74頁(yè)。LVS Comparison OptionProhibit Input SwappingLVSCHKxReduce Series ResistorsLVSCHKrProhibit parallel ReductionLVSCHKk第十三頁(yè)，共74頁(yè)。LVS Comparison OptionReduce Series CapacitorsLVSCHKaSeries MOS ReductionLVSCHKsCMOS Gate Re

14、ductionLVSCHKcLVSCHKlL不能做到AOI和OAI第十四頁(yè)，共74頁(yè)。LVS Parameter Comparison; lvs checkslvschkxre lpercent=0 wpercent=0 resval=1 capval=1 Specify the value tolerance for parameter comparisonLpercent: MOS length ratioWpercent: MOS width ratioResval: resistor value ratioCapval: capacitor value ratioW/l-percent

15、: MOS aspect ratio weffect=0.6: Corner effect to orthogonally bent gate第十五頁(yè)，共74頁(yè)。LVS Parameter Comparison; lvs checkslvschkxre lpercent=0 wpercent=0 resval=20 capval=1 例：將lvs中的resval改為20，重新對(duì)上一講的例子task1做LVS檢查(jinch)，看修改前后的錯(cuò)誤報(bào)告第十六頁(yè)，共74頁(yè)。修改(xigi)前的lvspr.lvs1 * * DISCREPANCY POINTS LISTING * * * DISCREP

16、ANCY 1 * DEV2 RES RP - RR0 : DEV6 RES P2 : X=-35.60 Y=9.70 OUT, VDD! OUT, VDD! SUB-TYPE = RP SUB-TYPE = P2 VALUE=15000.0 VALUE=13570.5 TOTAL 1 DISCREPANCY POINTS REPORTED這部分給出了schematic與layout不一致的地方：電阻(dinz)模型名和阻值不一致！第十七頁(yè)，共74頁(yè)。修改(xigi)后的lvspr.lvs1 * * DISCREPANCY POINTS LISTING * * * DISCREPANCY 1 *

17、 DEV2 RES RP - RR0 : DEV6 RES P2 : X=-35.60 Y=9.70 OUT, VDD! OUT, VDD! SUB-TYPE = RP SUB-TYPE = P2 TOTAL 1 DISCREPANCY POINTS REPORTED由于15k和13.57k之差小于resval規(guī)定的20%，所以認(rèn)為(rnwi)阻值通過LVS第十八頁(yè)，共74頁(yè)。.lvsLVS Debug LVS報(bào)告在lvspr.lvs中其結(jié)構(gòu)和內(nèi)容上一講已經(jīng)通過例子(l zi)來(lái)介紹過 LVS error比DRC error要難以debug 若設(shè)計(jì)中有子單元，一般先檢查底層子單元，待其全部正確

18、后再檢查頂層單元 LVS結(jié)果與指定的pin, label等密切相關(guān)，所以在指定時(shí)一定不要弄錯(cuò) 很多error都是相關(guān)的，一個(gè)error可能會(huì)連鎖導(dǎo)致很多error，故修正一個(gè)后馬上重做LVS 要debug LVS error，須熟知error types，所有的error type可在矛盾點(diǎn)列表(Discrepancy point listing)中查看第十九頁(yè)，共74頁(yè)。LVS Error TypesType 1: MATCHED NODE TO NO DEVICEType 2: MATCHED DEVICE TO UNMATCHED NODE總共(znggng)15種 error type

19、s第二十頁(yè)，共74頁(yè)。LVS Error TypesType 3: INCONSISTENTLY MATCHED DEVICEType 4: Matched Node to Extra Layout Devices第二十一頁(yè)，共74頁(yè)。LVS Error TypesType 5: Matched Node to Extra Schematic DevicesType 6: Matched Node to Unmatched Layout and Schematic Devices第二十二頁(yè)，共74頁(yè)。LVS Error TypesType 7: Other Unmatched Layout D

20、evicesType 8: Other Unmatched Schematic DevicesThis type of error indicate those layout devices which are either separated from rest of circuit or cannot be reached from initial correnspondence points or blocked by discrepancy pointsThis type of error indicate those schematic devices which are eithe

21、r separated from rest of circuit or cannot be reached from initial correnspondence points or blocked by discrepancy points第二十三頁(yè)，共74頁(yè)。LVS Error TypesType 9: Device Subtype MismatchType 10: Device Size Mismatch第二十四頁(yè)，共74頁(yè)。LVS Error TypesType 11: MOS Reversibility ErrorType 12: Device Substrate Connecti

22、on MismatchType 13: Device Power Connection Mismatch第二十五頁(yè)，共74頁(yè)。LVS Error TypesType 14: Reduced Layout Parallel Devices This type is for reference onlyType 15: Filtered-out Layout MOS Devices This type is for reference only第二十六頁(yè)，共74頁(yè)。LPE(Layout Parameter Extraction)Layoutstream outGDS II LPELPE Netli

23、stHspicePostlayout SimulationSchematicNetlistDRCLVS在LVS正確后，提取版圖(bnt)器件參數(shù)和寄生參數(shù)第二十七頁(yè)，共74頁(yè)。LPECDL NetlistGDS II DatabaseLOGLVSCDL OutLVSLOGIC.DATLPENET.DATStream OutLayoutSchematic修改(xigi)LPE Command filecd ./verifyPDRACULA:/g lpe:/取得(qd)LPE Command fileCdl out的網(wǎng)表，Stream out的gdsii file，Command file等最好都

24、放在一個(gè)專用(zhunyng)目錄下，如/project/verify第二十八頁(yè)，共74頁(yè)。LPE Netlist 做LPE時(shí)，schematic和layout中的元件類型、數(shù)量、相互間的連接關(guān)系必須一致，即電路拓?fù)浔仨氁恢?，否則會(huì)產(chǎn)生錯(cuò)誤(cuw) 若schematic和layout中元件的參數(shù)不一樣，則以layout中提取出來(lái)的值為準(zhǔn) 提取的參數(shù)主要包括元件參數(shù)（如mos管W/L，AD，PD，AS，PS，電阻阻值，電容容值等）和節(jié)點(diǎn)的寄生電容 提出出來(lái)的Netlist符合Hspcie格式第二十九頁(yè)，共74頁(yè)。LPE的例子(l zi)仍以第三講中的第一個(gè)版圖(bnt)設(shè)計(jì)作業(yè)為例lab:ta

25、sk1:schematiclab:task1:layout寄生提取(tq)與網(wǎng)表反標(biāo)注第三十頁(yè)，共74頁(yè)。查看(chkn)LPENET.DAT*MM0 OUT IN GND! GND! N L=0.80U W=6.00U AD=9.60P PD=15.20U AS=5.40P+ PS=7.80UMM0-1 OUT IN GND! GND! N L=0.80U W=6.00U AD=5.55P PD=7.85U AS=5.40P+ PS=7.80UMM0-2 OUT IN GND! GND! N L=0.80U W=6.00U AD=5.55P PD=7.85U AS=5.40P+ PS=7.8

26、0UMM0-3 OUT IN GND! GND! N L=0.80U W=6.00U AD=5.40P PD=7.80U AS=5.40P+ PS=7.80UMM0-4 OUT IN GND! GND! N L=0.80U W=6.00U AD=5.40P PD=7.80U AS=9.60P+ PS=15.20U*- TOTAL # OF MOS TRANSISTORS FOUND : 5*- COMMENTED : 0原來(lái)netlist里沒定義的，根據(jù)版圖新提出(t ch)來(lái)的參數(shù)須為0！否則表示(biosh)layout和schematic中的MOS管沒有完全對(duì)應(yīng)好第三十一頁(yè)，共74頁(yè)。寄

27、生(jshng)提取 - 晶體管MM0MM0-4h1h2w對(duì)于MM0的D端：AD w*h1 PD 2w+2h1對(duì)于MM0-1的D端：AD w*h2 PD w+h2其他(qt)類推MM0-1第三十二頁(yè)，共74頁(yè)。查看(chkn)LPENET.DAT* RESISTORS PARAMETERS FROM : 7RESXREF*RR0 OUT VDD! R 1.35705E04*- TOTAL # OF RESISTORS FOUND : 1*- COMMENTED : 0須為0！第三十三頁(yè)，共74頁(yè)。查看(chkn)LPENET.DAT* CAPACITORS PARAMETERS FROM :

28、7CAPXREF* CAPACITORS PARAMETERS FROM : 7CAPXMER*C1 OUT GND! 1.10627E-15C2 IN GND! 3.07552E-15C3 OUT GND! 1.03680E-16C4 OUT GND! 2.07360E-16*- TOTAL # OF CAPS FOUND : 4*- COMMENTED : 0*.ENDS原來(lái)(yunli)Schematic中沒有的，根據(jù)layout提出出來(lái)的電路節(jié)點(diǎn)寄生電容第三十四頁(yè)，共74頁(yè)。PRE(Parasitic Resistance Extraction) 從上面的LPENET.DAT可知，lp

29、e中只給出了提取元件參數(shù)和節(jié)點(diǎn)寄生電容的操作 為了更精確地模擬電路工作，除了提取元件參數(shù)和節(jié)點(diǎn)寄生電容外，還需提取寄生電阻(dinz)，即PRE 上華提供了PRE command file，實(shí)際上是在lpe的基礎(chǔ)上，增加了提取寄生電阻(dinz)的操作 仍以第三講中的第一個(gè)版圖作業(yè)為例第三十五頁(yè)，共74頁(yè)。PRECDL NetlistGDS II DatabaseLOGLVSCDL OutLVSLOGIC.DATPRENET.DATStream OutLayoutSchematic修改(xigi)PRE Command filecd ./verifyPDRACULA:/g pre:/取得(qd

30、)PRE Command fileCdl out的網(wǎng)表，Stream out的gdsii file，Command file等最好(zu ho)都放在一個(gè)專用目錄下，如/project/verify第三十六頁(yè)，共74頁(yè)。查看(chkn)PRENET.DAT*MM0 OUT:5 IN:9 GND! GND! N L=0.80U W=6.00U AD=9.60P PD=15.20U AS=5.40P+ PS=7.80UMM0-1 OUT:7 IN:10 GND! GND! N L=0.80U W=6.00U AD=5.55P PD=7.85U+ AS=5.40P PS=7.80UMM0-2 OUT

31、:7 IN:11 GND! GND! N L=0.80U W=6.00U AD=5.55P PD=7.85U+ AS=5.40P PS=7.80UMM0-3 OUT:9 IN:12 GND! GND! N L=0.80U W=6.00U AD=5.40P PD=7.80U+ AS=5.40P PS=7.80UMM0-4 OUT:9 IN:13 GND! GND! N L=0.80U W=6.00U AD=5.40P PD=7.80U+ AS=9.60P PS=15.20U*- TOTAL # OF MOS TRANSISTORS FOUND : 5*- COMMENTED : 0須為0！否則表

32、示layout和schematic中的MOS管沒有完全(wnqun)對(duì)應(yīng)好注意MOS管D、G端的(dund)節(jié)點(diǎn)名第三十七頁(yè)，共74頁(yè)。查看(chkn)PRENET.DAT* RESISTORS PARAMETERS FROM : 7RESXREF*RR0 OUT:12 OUT:4 R 3.39263E03RR0-1 OUT:13 OUT:14 R 3.39263E03RR0-2 OUT:16 OUT:15 R 3.39263E03RR0-3 OUT:17 VDD! R 3.39263E03*- TOTAL # OF RESISTORS FOUND : 4*- COMMENTED : 0注意要

33、考慮電阻端口間的寄生，故沒有象LPE那樣(nyng)reduce為一個(gè)電阻第三十八頁(yè)，共74頁(yè)。查看(chkn)PRENET.DAT* RESISTORS PARAMETERS FROM : 7RESPREF*R10 OUT OUT:2 4.53497E-02R11 OUT OUT:3 6.98120E-02R12 OUT:2 OUT:4 7.01360E-02R13 OUT:3 OUT:6 1.09479E-01R14 IN IN:2 6.41667E-02R15 OUT:5 OUT:6 5.08458E-02R16 OUT:12 OUT:13 1.88889E-01*R17 GND! GN

34、D!:3 1.02778E-01R18 OUT:6 OUT:8 2.21308E-01R19 IN:2 IN:3 3.54167E-02*R20 GND!:2 GND!:3 2.11111E-01*R21 GND!:3 GND!:5 6.56950E-02提取(tq)出了寄生電阻！寄生電阻(dinz)部分（1）對(duì)照版圖，結(jié)合前面MOS管的節(jié)點(diǎn)，仔細(xì)分析這些電阻的分布，找出提取的規(guī)律參考pre command file第三十九頁(yè)，共74頁(yè)。查看(chkn)PRENET.DATR22 OUT:14 OUT:15 1.88889E-01R23 OUT:7 OUT:8 5.08458E-02R24 I

35、N:3 IN:4 3.54167E-02R25 OUT:8 OUT:10 2.22724E-01*R26 GND!:4 GND!:5 2.38114E-01R27 IN:4 IN:5 3.33333E-02*R28 GND!:5 GND!:7 8.89198E-02R29 OUT:16 OUT:17 1.88889E-01R30 IN:5 IN:6 3.33333E-02R31 OUT:9 OUT:10 5.59105E-02R32 IN:6 IN:7 1.66925E-01*R33 GND!:6 GND!:7 2.30169E-01*R34 VDD! VDD!:3 1.40120E-01寄生

36、電阻(dinz)部分（2）第四十頁(yè)，共74頁(yè)。查看(chkn)PRENET.DATR35 IN:7 IN:8 2.29544E-01*R36 VDD!:2 VDD!:3 1.39566E-01R37 IN:2 IN:9 2.62500E01R38 IN:3 IN:10 2.62500E01R39 IN:4 IN:11 2.62500E01R40 IN:5 IN:12 2.62500E01R41 IN:6 IN:13 2.62500E01R42 OUT OUT:11 7.70667E-02R43 IN:8 IN:14 1.58400E-01*- TOTAL # OF RESISTORS FOUN

37、D : 34*- COMMENTED : 8寄生(jshng)電阻部分（3）寄生(jshng)部分不為0并不表示layout與schematic沒有對(duì)應(yīng)好第四十一頁(yè)，共74頁(yè)。查看(chkn)PRENET.DATC1 OUT GND! 1.75988E-16C2 IN GND! 8.06400E-17C3 IN:2 GND! 3.21120E-16C4 IN:3 GND! 3.21120E-16C5 IN:4 GND! 3.18816E-16C6 IN:5 GND! 3.18816E-16C7 IN:6 GND! 2.63520E-16C8 IN:7 GND! 6.63552E-16C9 IN

38、:8 GND! 2.88990E-16C10 IN:9 GND! 5.18400E-17C11 IN:10 GND! 5.61600E-17C12 IN:11 GND! 5.61600E-17C13 IN:12 GND! 5.18400E-17C14 IN:13 GND! 5.18400E-17*C15 VDD!:2 GND! 1.48598E-15*- TOTAL # OF CAPS FOUND : 15*- COMMENTED : 1寄生電容部分(b fen)寄生部分不為0并不表示layout與schematic沒有(mi yu)對(duì)應(yīng)好第四十二頁(yè)，共74頁(yè)。PRENET.DAT中的問題(w

39、nt) 沒有提取(tq)contact和via的寄生電阻 沒有提取(tq)S、D區(qū)的寄生電阻 沒有提取(tq)Gate上的電阻第四十三頁(yè)，共74頁(yè)。PRENET.DAT中的問題(wnt)element diopb ndio dptap dnsdg;n+/pwell dioPARASITIC RESA rmet1 m1trmATTRIBUTE RESA 5E-02PARASITIC RESB rpoly ptrmATTRIBUTE RESB 3.5E01PARASITIC RESC rmet2 m2trmATTRIBUTE RESC 4E-02PARASITIC CAPA m1poly1 m1t

40、rm ptrm ; Metal1 to poly1 capacitor &查看(chkn)lpe command file，找到如下定義寄生電阻的一段，分析問題的原因：具體資料可參考cadence在線(zi xin)幫助文檔關(guān)于dracula/lpe和pre那一塊，可試著去修改command file，來(lái)解決上述問題第四十四頁(yè)，共74頁(yè)。關(guān)于(guny)LPE和PRE 寄生提取需要工藝(gngy)廠商提供的工藝(gngy)參數(shù)來(lái)支持，如方塊電阻，單位面積電容等 一般來(lái)說(shuō)，在合理的版圖設(shè)計(jì)下（contact和via打得比較多比較均勻），寄生電容影響比較大，寄生電阻影響比較小 對(duì)于大作業(yè)，開關(guān)電容

41、電路，要求是版圖設(shè)計(jì)后做LPE提取就可以了；但是在版圖設(shè)計(jì)中要注意合理打孔的問題第四十五頁(yè)，共74頁(yè)。Post layout simulation提取(tq)前：M_U0 OUT IN 0 0 nm L=0.80U W=6.00U M=5提取(tq)后： MM0 OUT IN 0 0 nm L=0.80U W=6.00U M=1 AD=9.60P PD=15.20U AS=5.40P PS=7.80U如右圖做AC分析，分別(fnbi)用提取前和提取后的網(wǎng)表第四十六頁(yè)，共74頁(yè)。Post layout simulation提取前提取后AC分析結(jié)果Problem: 提取提取(tq)寄生后電路工作速

42、度反而快寄生后電路工作速度反而快了？了？第四十七頁(yè)，共74頁(yè)。Post layout simulation subckt element 0:m_u0 0:mm0 0:mm0-1 0:mm0-2 0:mm0-3 0:mm0-4 model 0:nm 0:nm 0:nm 0:nm 0:nm 0:nm region Saturati Saturati Saturati Saturati Saturati Saturati id 214.6697u 42.9339u 42.9339u 42.9339u 42.9339u 42.9339u cdtot 30.3121f 6.9274f 3.7862f

43、3.7862f 3.7322f 3.7322f cgtot 55.4146f 11.0829f 11.0829f 11.0829f 11.0829f 11.0829f cstot 87.5586f 14.3197f 14.3197f 14.3197f 14.3197f 18.8477f cbtot 71.5139f 11.9758f 8.8346f 8.8346f 8.7805f 13.3085f cgs 39.6775f 7.9355f 7.9355f 7.9355f 7.9355f 7.9355f cgd 8.8547f 1.7709f 1.7709f 1.7709f 1.7709f 1.

44、7709f提取(tq)前的MOS管漏極電容比提取(tq)后要大？查看(chkn).lis文件內(nèi)容第四十八頁(yè)，共74頁(yè)。Post layout simulationMOSFET Diode Model : ACMArea calculation Method (ACM) Parameter Allows for the Precise Control of Modeling Bulk-Source & Bulk_Drain Diodes within MOSFET ModelsACM=0、1、2或或3，對(duì)應(yīng)的，對(duì)應(yīng)的AD, PD, AS, PS的計(jì)算方法的計(jì)算方法也不同也不同檢查上華模型庫(kù)檢查上

45、華模型庫(kù)csmc.lib，在，在mos管管model部分發(fā)現(xiàn)如下部分發(fā)現(xiàn)如下(rxi)參數(shù)：參數(shù)：acm = 2 ldif = 0.00 hdif = 6.00e-07 第四十九頁(yè)，共74頁(yè)。Post layout simulationLDIFHDIFWeffACM=2時(shí)的面積和周長(zhǎng)時(shí)的面積和周長(zhǎng)(zhu chn)計(jì)算方法（當(dāng)計(jì)算方法（當(dāng)AD，PD等參數(shù)沒有指定時(shí)）：等參數(shù)沒有指定時(shí)）： ADeff = 2HDIFWeff PDeff = 4HDIF+2Weff若若AD，PD等已給定，則按給定值計(jì)算等已給定，則按給定值計(jì)算上華：LDIF=0HDIF=0.6u第五十頁(yè)，共74頁(yè)?？偟腁D_tot

46、al=ADMPost layout simulation修改提取前的網(wǎng)表，按照修改提取前的網(wǎng)表，按照hdif的值來(lái)計(jì)算出面積和周長(zhǎng)，然后加到的值來(lái)計(jì)算出面積和周長(zhǎng)，然后加到MOS管網(wǎng)表中：管網(wǎng)表中：M_U0 OUT IN 0 0 nm L=0.80U W=6.00U M=5+ AD=7.2p PD=14.4u AS=7.2p PS=14.4u仿真并查看仿真并查看.lis文件內(nèi)容，可知文件內(nèi)容，可知M_U0的的cdtot， cstot等跟修改之前等跟修改之前的仿真結(jié)果完全一樣。的仿真結(jié)果完全一樣。說(shuō)明：說(shuō)明：1）當(dāng)）當(dāng)MOS管沒加管沒加AD，PD等參數(shù)時(shí)，不表示沒有寄生等參數(shù)時(shí)，不表示沒有寄生2

47、）不指定參數(shù)，）不指定參數(shù)，AD，PD等則按照模型等則按照模型(mxng)給出的給出的hdif進(jìn)行計(jì)進(jìn)行計(jì)算算第五十一頁(yè)，共74頁(yè)。Post layout simulation計(jì)算提取出來(lái)計(jì)算提取出來(lái)(ch li)的的MM0MM0-4的的AD，PD等平均值，并賦予等平均值，并賦予M_U0，這樣修改提取前的網(wǎng)表為：，這樣修改提取前的網(wǎng)表為：M_U0 OUT IN 0 0 nm L=0.80U W=6.00U M=5+ AD=6.3p PD=9.3u AS=6.24p PS=9.28u仿真并查看仿真并查看.lis文件內(nèi)容，可知文件內(nèi)容，可知M_U0的的cdtot， cstot等跟提取后等跟提取后M

48、M0MM0-4對(duì)應(yīng)項(xiàng)之和一樣。對(duì)應(yīng)項(xiàng)之和一樣。提取前提取后修改(xigi)的網(wǎng)表與提取的網(wǎng)表AC分析結(jié)果對(duì)比第五十二頁(yè)，共74頁(yè)。Post layout simulation練習(xí)練習(xí)(linx)：根據(jù)經(jīng)驗(yàn)，預(yù)先估算出各：根據(jù)經(jīng)驗(yàn)，預(yù)先估算出各MOS管版圖設(shè)管版圖設(shè)計(jì)后的計(jì)后的AD, PD, AS, PS，把它們加入網(wǎng)表，進(jìn)行，把它們加入網(wǎng)表，進(jìn)行AC分分析，對(duì)比修改前后的分析結(jié)果析，對(duì)比修改前后的分析結(jié)果第五十三頁(yè)，共74頁(yè)。Post layout simulation LPE和postsim可更精確的模擬電路特性 對(duì)于(duy)特征尺寸比較大的工藝，wire delay遠(yuǎn)小于cell del

49、ay（特殊wire除外） 在schematic設(shè)計(jì)階段，就可根據(jù)layout設(shè)計(jì)經(jīng)驗(yàn)給MOS管定義AD，PD等參數(shù)，以較精確預(yù)測(cè)layout設(shè)計(jì)后的電路性能第五十四頁(yè)，共74頁(yè)。Schematic分層設(shè)計(jì)(shj)PW=10uNW=4uM=1PW=10uNW=4uM=2PW=10uNW=4uM=4VinVout所有(suyu)MOS管子用最小溝道長(zhǎng)度問題：各反相器中的元件參數(shù)(cnsh)不一樣，需要畫多個(gè) inv schmematic和symbol？一個(gè)例子：CL第五十五頁(yè)，共74頁(yè)。Schematic分層設(shè)計(jì)(shj)解決方法：用pPar參數(shù)設(shè)定，避免(bmin)電路單元的多重建立PWPLN

50、WNLMM參數(shù)(cnsh)化單元第五十六頁(yè)，共74頁(yè)。單元參數(shù)(cnsh)設(shè)定第一步：打開inv:schematic，用pPar方式(fngsh)設(shè)定PMOS和NMOS的CDF參數(shù)；如PMOS：第五十七頁(yè)，共74頁(yè)。單元參數(shù)(cnsh)設(shè)定pPar參數(shù)(cnsh)設(shè)定后的inv:schematic第五十八頁(yè)，共74頁(yè)。單元(dnyun)參數(shù)設(shè)定第二步：check&save - 自動(dòng)創(chuàng)建symbol - 修改(xigi)symbol view（見第四講課件） ：第五十九頁(yè)，共74頁(yè)。單元(dnyun)參數(shù)設(shè)定第三步：給inv:symbol增加(zngji)CDF參數(shù) 1) 在CIW窗口，點(diǎn)擊 tools - CDF - Edit2) 在彈出的 Edit Component CDF 窗口，用browse按鈕選擇lab:inv:symb