1、第十章可測試性設計OutlinesOverview of IC TestingFault ModelingAutomatic Test Pattern Generation (ATPG)Design-for-test (DFT) techniquesScan chain techniqueMBISTBoundary ScanVerification vs. Test VerificationVerifies correctness of design.Performed by simulation, hardware emulation, or formal verification, etc

2、.Performed once prior to manufacturing.Responsible for quality of design.TestVerifies correctness of manufactured hardware.Two-part process:1. Test generation: software process executed once during design2. Test application: electrical tests applied to hardwareTest application performed on every man

3、ufactured device.Responsible for quality of devices. Testing PrincipleThree basic elementA known input StimulusA known stateA known expected responseAutomatic Test Equipment (ATE)Overview of IC TestingWaferFabricationDie AssemblyFinal TestReliabilityStressClass ProbeDie Sort ProbeParameter VtP VtN I

4、gS IdS Leff Weff Res . Coverage leakage memory Core .Coverage DC AC Digital Analog Speed Temp Power .Qualification Burn-in Temp-Cycle HVST ESD Latch-up .Package BGA QFP PGA TAB CSP SIP MCM .DesignTest ChallengesReduce the cost of test Reduce the vector data sizeReduce the tester sequencing complexit

5、yReduce the cost of test equipment Reduce the test timeIncrease the defect coverageHow many function test patterns can cover all the devices?OutlinesOverview of IC TestingFault ModelingAutomatic Test Pattern Generation (ATPG)Design-for-test (DFT) techniquesTypes of Test Vector SetsExhaustiveApply ev

6、ery possible input vectorA long time!FunctionalTest every function of the deviceHow to guarantee the coverage?Fault Model DerivedFind a test for every “modeled” faultIndustry practice currentlyWhy Model Faults?Fault model identifies target faultsFault model makes analysis possibleEffectiveness measu

7、rable by experimentsDefect & Fault Modeling DefinitionDefect: Physical abnormally fabricated die E.g. missing/extra materialFault: behavior difference due to a defect E.g. input stuck-at 1, output slow-to-riseError: machine failure due to a fault E.g. system functional failureBug functional failure

8、caused by design problem E.g. system functional failureDefect: short to the grandFault: signal b stuck at logic 0Error: happens when a=1 b=1ExampleFault ModelsFault models are typically defined on a structure basisDifferent fault models for digital logic, memories and analog circuitTypical fault mod

9、elsSingle stuck-at faultsTransistor open/short faultsBridging faultsDelay faultsMemory faultsAnalog faultsStuck-AT FaultsWhat is stuck-at fault?Applicable to any physical defect manifesting as a signal that is stuck at a fixed logic levelOne stuck-at fault can model more than one kind of defectTrans

10、ition Delay FaultModel large transition delay slow to rise or slow to fall transitionan interconnect signal has a greater than normal propagation delay associated with itThe model behaves as stuck at fault for a certain period of timePath Delay FaultIt models defects in circuit pathUnlike transition

11、 delay fault, path delay faults do not have localized fault sites.Associated with testing the AC performance of specific pathsTypically critical pathMemory Faults 011100Stuck-AT- 0Stuck-AT- 1OR BridgingAND Bridging01Transition / 0Transition / 10111Reset CouplingSet Coupling1010Inversion CouplingInve

12、rsion Coupling11101PassiveNeighborhoodPattern SensitiveActiveNeighborhoodPattern Sensitive11010AdrEAdrEAdrEAdrEAdrEVarious FaultsWith Address DecoderMemory Fault cont.Neighborhood pattern sensitive faultOutlinesOverview of IC TestingFault ModelingAutomatic Test Pattern Generation (ATPG)Design-for-te

13、st (DFT)ScanFault CoverageFault coverageThe percentage of total faults for which test patterns have been generated Fault Coverage = 100 XNumber of Detected FaultsTotal Number of Faults in the CUTFault coverage is influenced by Testability of the circuit Quality of applied patternsTest Generation Def

14、initionsTest vectorsAn input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary outputAutomatic test pattern generationWith the build-in DFT circuit, test vectors are generated automatically Vector Generation Using ATPG ToolRead in netlist with scan c

15、hain connectedRead in IP and standard-cell library modelRead in STIL test protocol file, generated by DFT compiler tool. (STIL - Standard Test Interface Language for Digital Test Vectord, IEEEStd. 1450.0-1999)Check DRC and make any necessary correctionsPrepare design for ATPG, setup fault list, anal

16、yze buses for contention and set the ATPG optionsGenerate vectorsReview the test coverage and re-run ATPG if necessaryCompress the vectorsConvert vector to ATE vector formatSave test vectors and fault listOutlinesOverview of IC TestingFault ModelingAutomatic Test Pattern Generation (ATPG)Design-for-

17、test (DFT) techniquesScan chain MBISTBoundary scanWhat is DFT?Apply design-for-testability techniques to the device during the design phase to assist with the test process, quality measurement and the vector generationTest structures is designed (added) into the deviceTraditional design and test flo

18、wAdvanced design and test flowWhy Add test Logic?Motivation: Test generation complexity increases exponentially with the size of the circuitReasons: to increase the test coverage and to reduce the time it takes to qualify the partPro & Con Perceptions of DFTProsEasy generating vectorsEasy diagnosis

19、& debuggingEnables deterministic measure of qualityReduces the cost of testConsAdds complexity to design methodologyImpacts design power & package pinsImpacts design speed or performanceAdds to silicon areaReduce yieldPopular DFT Techniques for SoC TestingScanDealing with sequential logic circuitCom

20、monly used for testing digital logicBIST (Build-in-Self-Test) Commonly used to testing memory blocks MBISTAlso can be found for testing processor Logic BISTAlso can be found for testing analog circuit Analog BISTBoundary Scan For testing I/O connection on boardIt also is a common interface standard

21、for system debugging on boadScan ChainSequential Logic Hard to Test!In reality, the sequential algorithm method is usually very complicated and require:One or more clock pulses to launch the test vector to the faulty siteOne or more clock cycles to propagate the fault effectIn general, need a sequen

22、ce of patterns to detect a fault!A better solution is to insert scan circuit scan design techniqueSteps of Scan Design Convert flip-flops (FF) to scan flip-flops (SFF)Connect SFF to scan chainsIn normal mode: SFF behave as usualIn scan mode: SFF behave as shift registerScan Flip-Flop (SFF)Scan cell:

23、 Mux-D Scan Flip Flop typeDFFSDFFThe most widely accepted scan styleScan cell will cause larger area, larger setup time, more power consumptionScan Chain ConnectionReplace all FF with SFFConnect to scan chainsTest Sequential Logic Using Scan SFFs & scan chain help to initialize nodes and capture res

24、ults controllability & observabilityTools for Scan Synthesis and ATPG Fully supported by EDA toolsScan insertionDFT compiler from SynopsysDFT Advisor from MentorTest vector generation (ATPG)TetraMAX from SynopsysFastScan from MentorTest pattern verificationSTA is used to check the scan test timing i

25、n scan modeSimulation is used to verify ATPG patternScan Design RulesScan design rules govern the controllability and observability of scan design (fault coverage)Scan design rule checking (DRC) provides you with feedback on the testability of your design (Does the signals can path the scan chain?)B

26、asic Scan Design RulesUse only Mux-D type of flip-flops for all state variablesAll clocks/reset must be controlled from PIs.Clocks must not feed inputs of flip-flops (to D pin of FF)Do not use tri-state bus design or disable the tri-state buffer during scan test Example: Dealing with Tri-state bus T

27、ri-state busDuring scan shifts, multiple drivers on a bus may drive the bus simultaneously which causes bus contention problem or no driver on the bus lead to a floating bus.Fix:Mux added to make the bus controllable during scan modeExample: Dealing with Black BoxBypass Black BoxAnalog blocks, memor

28、ies, hardmacrosExample: Memory Block Interface Bypass Memory Block: adding shadow register (Optional)If the chip-testing goals include scan testing for AC coverage (transition and path delay), then the previous bypass method may not be sufficient. To more emulate the memory pathway, a register is pl

29、aced in the transparent data pathShadow register scan chain is inserted by toolGeneral DFT Consideration for SoC Design Avoid asynchronous design style. Limit the number of different clock domains in a chip. For multiple clocks, make the FFs in each individual clock domain form their own scan chains

30、 to avoid the bigger variation in skew. Or add muxing at the clock source, so that only one clock is used during scan-mode and clock tree synthesisReplace any internally-generated/divided clocks/reset with scan clocks/reset from PIs during testingHigh fanout signal pin, Scan_enable, should be taken

31、care by synthesis tools Prepare Scan wrappers for non-synthesizable modules, such as memory blockAvoid long scan chain, max 1000FFs per chainAvoid power consumption issue, may need to separate the whole chip to few scan modes and the clocks to the module not being tested should be disabledScan chain

32、 reordering may need in layout stageGeneral DFT Consideration - cont Scan Overhead: Scan path impact timing, area and power goalsModerate area overhead about 10%, speed 5%Multiplexer delay added in combinational path; approx. two gate-delaysFlip-flop output loading due to one additional fanout; appr

33、ox. 5-6%At least one extra pins for scan mode signals: scan_mode, scan_enable, scan_clk, scan_reset, scan_in, scan_outGeneral DFT Consideration cont.Scan Design FlowTypical Quality Requirements 98% single stuck-at fault coverage 100% interconnect fault coverageReject ratio 1 in 100,000Please check t

34、he test coverage after scan insertion as well as after ATPGFix possible DFT violationSummary Various defects (faults) exist in chipsFault models describe the faultsDFT deals with ways for improving testabilityDFT are essential to an efficient and successful testingMemory Build-in-self test (MVIST)Im

35、portance of Memory TestMemory is the most dense physical structure, making them more sensitive to defectsOn-chip memory is getting bigger for SoC Memory ModelThe functional memory model contains three main partsAddress decoderMemory cell arrayRead/write control logicBasic memory faults:stuck-attrans

36、itioncouplingNeighborhood pattern sensitiveMemory Built In Self Test (MBIST)General test data on-chipCompare or compress data on-chipUsed to detect faults in SRAM, ROM, SDRAM and FLASHMemory Built In Self Test (MBIST)Components of BIST:Pattern generatorBIST controllerResponse analyzerBasic Test Port

37、sTest pin nameDescriptionBIST_MODETest Mode Select(used to select to mux logic)BIST_RESETTest Mode Select(Used to reset BIST logic)BIST_CLKTest ClockBIST_DONETest Data Out indicating test completeBIST_FAILTest Data Out indicating test fail Memory BIST AlgorithmsCheckerboardMarch Data Retention TestC

38、heckerboard AlgorithmDetects stuck-at faults for memory cells and adjacent cell shortsThe algorithm divides the cells into two groups (cells_1 and cells_2), such that every neighboring cell is in a different group. The algorithm then writes (and reads) 0s into all cells in the cells_1 group and 1s i

39、nto all cells in the cells_2 groupMarch AlgorithmFirst presented at the ITC in 1982, the March algorithm, and its modifications, is now the most popular algorithm for memory testing.Test sequence（9n）(w0) (r0,w1) (r1,w0) (r0, w1) (r1, w0)The March Algorithm detects the following faults:stuck-attransi

40、tioncoupling - unlinked idempotent and inversion, and other coupling faults on bit-oriented addressesAlgorithmMATSMATS+MATS+MARCH XMARCHCMARCH AMARCH YMARCH BDescription (w0); (r0, w1); (r1) (w0); (r0, w1); (r1, w0) (w0); (r0, w1); (r1, w0, r0) (w0); (r0, w1); (r1, w0); (r0) (w0); (r0, w1); (r1, w0)

41、; (r0, w1); (r1, w0); (r0) (w0); (r0, w1, w0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) (w0); (r0, w1, r1); (r1, w0, r0); (r0) (w0); (r0, w1, r1, w0, r0, w1); (r1, w0, w1); (r1, w0, w1, w0);(r0, w1, w0) Modified March AlgorithmMarch Test ComplexityAlgorithmMATSMATS+MATS+MARCH XMARCH CMARCH A

42、MARCH YMARCH BComplexity4n5n6n6n10n15n8n17nRetention testing verifies if memory cells can retain their initial contents for a certain period of time. The time period can vary from 10 - 80 ms depending mainly on the manufacturing process and the ambient temperature during the test applicationThe inse

43、rted delay can refer to the Algorithm March C and CheckerboardData Retention TestShare controller with memory blocksMemory Wrapper for Logic ScanToolsCommercial tools are available for MBIST design and ATPGmBISTArchitect from MentorSoCBIST from SynopsysBoundary ScanWhats the purpose of Boundary Scan

44、? Test the IC connection on the PCB (printed circuit board test):Missing devices, Damaged devices, Open and short circuits, Misaligned devices, Wrong devices Testing the integrated circuit itself (debugging)Observing or modifying circuit activity during the components normal operationIn-system progr

45、amming (system level application)Allowing programming programmable devices, such as CPLDs and flash memories, on the board, after PCB assembly Example: Test IC Connection on PCBTesting the interconnections of chips on a printed circuit board or other substrateICs on one boardIEEE Standard 1149.1Deve

46、loped in the mid-1980s by the JTAG group (Joint Test Action Group) Solve physical access problems on PCBs caused by increasingly crowded assemblies Defines test access ports, architecture and operation of boundary scanBecome industry standard IEEE 1149.1 since 1990IEEE Std 1149.1 Device Architecture

47、Test Access Port (TAP)TAP controller with inputs TCK and TMSInstruction Register (IR)Bypass RegisterIdentification register Boundary-scan registerBasic Functions of Boundary Scan ArchitectureParallel taking-over of test vectors into the Boundary Scan cells (sample) Serial shifting in of test vectors

48、 and simultaneous shifting out of test vectors that were taken over (shift) Parallel application of inserted test vectors to the circuit parts to be tested (update) Test/ stimulation of the inner circuitry (internal test) Test/ stimulation of outside signals connected to a circuit (external test) JT

49、AG PinsTest pin nameDescriptionTDITest Data In(used to receive Serial test instruction and data)TMSTest Mode Select(Used to sequence the test controllers state machine)TCKTest ClockTDOTest Data OutTRSTTest ResetTAP ControllerTest Access Port (TAP) Controller Control all test logics operationsTAP Con

50、troller - contFinite State Machine of TAP ControllerAll test logics operation is controlled by TAP controllerBoundary Scan Circuit in DetailBoundary Scan Register (Cell)A multipurpose memory element called a “boundary scan cell” or “boundary scan register” PI - parallel in signal PO - parallel output signalSI - serial in signalSO - serial out signalInstruction RegisterAt least 2 bits longThe instruction register has a shift section that can be connected to TDI and TDO, and a hold section, which holds the current instruct