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Collector:Liang-BiChenProgress:CH2Date:Mar13,20071/15/2023Ch2為何通用型處理器具有單位成本很低,技術(shù)很優(yōu)良,開發(fā)者可以減少大量的time-to-market的時(shí)間,這樣是否代表客製化的處理器市場(chǎng)將面對(duì)很大的壓力?1/15/20232AmethodologyforthedesignofAHBbusmasterwrappersCh2(CH2.6)我們要怎麼知道從哪個(gè)地方下手去optimizesingle-processor?Flip-flop有所謂edge-triggered的特性，而edge-triggered又可分為rising-edge-triggered和falling-edge-triggered想問說(shuō)這兩種在實(shí)現(xiàn)上(電路設(shè)計(jì))是否有所不同？還有就是在實(shí)際運(yùn)用上是否有差別？例如說(shuō)哪方面的設(shè)計(jì)用rising-edge-triggered會(huì)比f(wàn)alling-edge-triggered好)1/15/20233AmethodologyforthedesignofAHBbusmasterwrappersCh2課本p38頁(yè)的figure2.8(b)其中next-stateandcontrollogic有一個(gè)output到datapath的register和functionalunits是代表說(shuō)這個(gè)output會(huì)影響到這兩個(gè)（register和functionalunits）的輸出嗎？那這樣的影響跟register和functionalunits兩者互相的輸出輸入有什麼差異？……aviewinsidethecontrolleranddatapathcontrollerdatapath……stateregisternext-stateandcontrollogicregistersfunctionalunits1/15/20234AmethodologyforthedesignofAHBbusmasterwrappersCh2同步清除、非同步清除的各別的特色好壞，

課本是說(shuō)clearcontrollinesareasynchronous

p.36

但synchronous電路控制上不是比較容易嗎?1/15/20235AmethodologyforthedesignofAHBbusmasterwrappersCh2AboutthereasonandexampleforstartingwithanFSMDbutnotprogramwhichisdescribedin2.5(pg44),thesendersend4bitsatatime,shouldnotthatistheresponsibilityforthesendertosendtheansweratonetime?Ifthatso,thennobridgeisneeded.

ProblemSpecificationBridgeAsingle-purposeprocessorthatconvertstwo4-bitinputs,arrivingoneatatimeoverdata_inalongwithardy_inpulse,intoone8-bitoutputondata_outalongwithardy_outpulse.Senderdata_in(4)rdy_inrdy_outdata_out(8)ReceiverclockFSMDWaitFirst4RecFirst4Startdata_lo=data_inWaitSecond4rdy_in=1rdy_in=0RecFirst4Endrdy_in=1RecSecond4Startdata_hi=data_inRecSecond4Endrdy_in=1rdy_in=0rdy_in=1rdy_in=0Send8Startdata_out=data_hi&data_lordy_out=1Send8Endrdy_out=0Bridgerdy_in=0Inputsrdy_in:bit;data_in:bit[4];Outputsrdy_out:bit;data_out:bit[8]Variablesdata_lo,data_hi:bit[4];1/15/20236AmethodologyforthedesignofAHBbusmasterwrappersCh2(Ch2.6OptimizingCustomSingle-PurposeProcessors)Optimize的processes最出是從OptimizingtheOriginalProgram開始，我們要如何知道Program是Optimize以及最後的FSM是Optimize。在演算法的課程我們知道當(dāng)問題比較大的時(shí)候可以用Transformation到其他已經(jīng)證明出為Optimize的問題上。那像Figure2.9GCD可以再簡(jiǎn)化其algorithm?GCD(a)black-boxviewx_iy_id_ogo_i0:intx,y;1:while(1){2:while(!go_i);3:x=x_i;4:y=y_i;5:while(x!=y){6:if(x<y)7:y=y-x;else8:x=x-y;}9:d_o=x;}y=y-x7:x=x-y8:6-J:x!=y5:!(x!=y)x<y!(x<y)6:5-J:1:1!1x=x_i3:y=y_i4:2:2-J:!go_i!(!go_i)d_o=x1-J:9:(c)statediagram1/15/20237AmethodologyforthedesignofAHBbusmasterwrappersCh2在FSMD上，conditionstateandjoinstate，兩者皆無(wú)動(dòng)作。不過視conditionstate為一種判斷式，但joinstate確看不出有何功能在?如fig2.10(b),為何不在loop-body-statement之後直接forward到conditionstate做下一次的判斷，而非要經(jīng)過一個(gè)沒有任何動(dòng)作的joinstate?如fig2.8(c),在c1,c2,c3stmts之後，為何不能直接nextstatement而非要先經(jīng)過joinstate呢?Loopstatementwhile(cond){loop-body-statements}nextstatementloop-body-statementscondnextstatement!condJ:C:

Branchstatementif(c1)

c1stmtselseifc2c2stmtselseotherstmtsnextstatementc1c2stmts!c1*c2!c1*!c2nextstatementothersc1stmtsJ:C:(b)(c)1/15/20238AmethodologyforthedesignofAHBbusmasterwrappersEmbeddedSystemCourse

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Collector:Liang-BiChenProgress:CH3Date:Mar13,20071/15/2023Ch31)請(qǐng)問管線技術(shù)如果在一些需要較長(zhǎng)的執(zhí)行時(shí)間的指令時(shí)是不是就無(wú)法發(fā)揮了?2)有關(guān)於定址模式,是不是如果資料大小很小時(shí),就直接使用immediate或是register-direct來(lái)提高效能?1/15/202310AmethodologyforthedesignofAHBbusmasterwrappersCh3Memoryarchitecture分成Harvard跟Princeton兩種架構(gòu),書上提到大部分的機(jī)器都用Princeton架構(gòu),是使用起來(lái)因?yàn)楸容^簡(jiǎn)單方便嗎?Harvard除了可以同時(shí)讀取指令跟資料外,還有其他的優(yōu)點(diǎn)嗎?1/15/202311AmethodologyforthedesignofAHBbusmasterwrappersCh3在Figure3.2的部份提到Harvard跟Princeton兩種memoryarchitectures，在大部分的機(jī)器都使用Princetonarchitecture，而快取記憶體的部份又提到它分成I-cache與D-cache，這不就是Harvardarchitecture，那在一般的機(jī)器裡面應(yīng)該同時(shí)存在一般記憶體跟快取記憶體，那意思是說(shuō)這兩種架構(gòu)也可以並存嗎？ProcessorProgrammemoryDatamemoryProcessorMemory(programanddata)HarvardPrinceton1/15/202312AmethodologyforthedesignofAHBbusmasterwrappersCh3關(guān)於課本第3.7章的selectingamicroprocessor，比較performance，課本是以Dhrystone的執(zhí)行次數(shù)或者M(jìn)IPS為評(píng)定依據(jù)，但就MIPS來(lái)說(shuō)，以每秒幾百萬(wàn)個(gè)instruction來(lái)評(píng)量效能的話，不同class的instruction可能會(huì)有不同的clockcycle數(shù)，又不同機(jī)器上的