數(shù)字系統(tǒng)設(shè)計(jì)與VHDL(第3版）數(shù)字系統(tǒng)設(shè)計(jì)與VHDL（第3版）第8章

VHDL設(shè)計(jì)進(jìn)階

8.1行為描述8.2數(shù)據(jù)流描述8.3結(jié)構(gòu)描述8.4三態(tài)邏輯設(shè)計(jì)8.5分頻器設(shè)計(jì)8.6乘法器設(shè)計(jì)8.7存儲(chǔ)器設(shè)計(jì)8.8流水線設(shè)計(jì)8.9資源共享設(shè)計(jì)8.10用鎖相環(huán)IP核實(shí)現(xiàn)倍頻和相移8.1行為描述可將VHDL對(duì)邏輯電路的建模和描述方式分為如下3種：（1）行為（Behavioural）描述。（2）數(shù)據(jù)流（DataFlow）描述或寄存器傳輸級(jí)（RTL）描述。（3）結(jié)構(gòu)（Structural）描述。所謂行為描述，就是只描述電路的行為和功能，不涉及電路硬件結(jié)構(gòu)，行為描述是對(duì)設(shè)計(jì)實(shí)體的數(shù)學(xué)抽象，只需關(guān)注輸入與輸出信號(hào)的行為關(guān)系，而無須花費(fèi)精力于設(shè)計(jì)結(jié)構(gòu)的具體實(shí)現(xiàn)?！纠?.2】用FORLOOP語(yǔ)句描述的7人表決電路。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYvote7ISPORT(vt:INSTD_LOGIC_VECTOR(7DOWNTO1);pass:OUTSTD_LOGIC);ENDENTITYvote7;ARCHITECTUREbehavOFvote7ISBEGINPROCESS(vt)VARIABLEsum:INTEGERRANGE0TO7;--定義贊成票變量BEGINsum:=0;FORiIN1TO7LOOP --FORLOOP語(yǔ)句IF(vt(i)='1')THENsum:=sum+1;IF(sum>=4)THENpass<='1';--超過半數(shù)表決通過ELSEpass<='0';ENDIF;ENDIF;ENDLOOP;ENDPROCESS;ENDbehav;8.2數(shù)據(jù)流描述數(shù)據(jù)流（DataFlow）描述側(cè)重于描述數(shù)據(jù)流的運(yùn)動(dòng)路徑和結(jié)果，數(shù)據(jù)流描述亦表示行為，同時(shí)也隱含結(jié)構(gòu)信息，有時(shí)也將數(shù)據(jù)流描述稱作寄存器傳輸級(jí)（RTL）描述。綜合器工具軟件都提供了將VHDL（或VerilogHDL）源碼轉(zhuǎn)換為RTL級(jí)原理圖的功能，便于設(shè)計(jì)者查看電路的RTL級(jí)實(shí)現(xiàn)框圖。用邏輯符號(hào)及邏輯方程式表達(dá)設(shè)計(jì)可看作數(shù)據(jù)流（DataFlow）描述，在有的設(shè)計(jì)中已知布爾代數(shù)表達(dá)式，就很容易將它轉(zhuǎn)換為VHDL的數(shù)據(jù)流表達(dá)式，轉(zhuǎn)換方法是用VHDL的邏輯運(yùn)算符置換布爾邏輯運(yùn)算符即可。例如，用OR置換“+”，用“<=”置換“=”，如方程式f=ab+cd轉(zhuǎn)換為f<=(aANDb)OR(cANDd)。例8.8用邏輯運(yùn)算符實(shí)現(xiàn)的1位全加器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfuadd_dfISPORT(a,b,cin:INSTD_LOGIC;sum,cout:OUTSTD_LOGIC);ENDfuadd_df;ARCHITECTUREdataflowOFfuadd_dfISBEGINsum<=aXORbXORcin;cout<=(aANDb)OR(bANDcin)OR(aANDcin);ENDdataflow;8.3結(jié)構(gòu)描述結(jié)構(gòu)描述，就是指在設(shè)計(jì)中，實(shí)例化已有的功能模塊，通過調(diào)用庫(kù)中的元件或已設(shè)計(jì)好的模塊來完成設(shè)計(jì)實(shí)體功能的描述。在結(jié)構(gòu)體中，描述只表示元件（COMPONENT）和元件（或模塊）之間的互連，就像網(wǎng)表一樣。當(dāng)調(diào)用庫(kù)中不存在的元件時(shí)，則必須首先進(jìn)行元件的創(chuàng)建，然后將其放在工作庫(kù)中，以供調(diào)用。例8.13結(jié)構(gòu)描述的1位全加器頂層設(shè)計(jì)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYfull_addISPORT(ain,bin,cin:INSTD_LOGIC;cout,sum:OUTSTD_LOGIC);ENDENTITYfull_add;ARCHITECTUREstructOFfull_addISCOMPONENThalf_add--將半加器定義為元件PORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDCOMPONENT;

例8.13結(jié)構(gòu)描述的1位全加器頂層設(shè)計(jì)。

COMPONENTor2hPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:half_addPORTMAP(a=>ain,b=>bin,co=>d,so=>e);--元件例化u2:half_addPORTMAP(a=>e,b=>cin,co=>f,so=>sum);u3:or2hPORTMAP(a=>d,b=>f,y=>cout);ENDARCHITECTUREstruct;例8.11半加器的VHDL描述。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_addISPORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDENTITYhalf_add;ARCHITECTUREoneOFhalf_addisBEGINso<=aXORb;co<=aANDb;ENDARCHITECTUREone;例8.12或門邏輯描述。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2hISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYor2h;ARCHITECTUREoneOFor2hISBEGINy<=aORb;ENDARCHITECTUREone;8.4三態(tài)邏輯設(shè)計(jì)例8.16三態(tài)門。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtrigateISPORT(en,a:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDtrigate;ARCHITECTUREoneOFtrigateISBEGINy<=aWHEN(en='1')ELSE'Z';ENDone;8.4三態(tài)邏輯設(shè)計(jì)例8.171位三態(tài)雙向緩沖器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYbidirISPORT(y:INOUTSTD_LOGIC;--y為雙向I/O端口en,a:INSTD_LOGIC;b:OUTSTD_LOGIC);ENDbidir;ARCHITECTUREoneOFbidirISBEGINy<=aWHEN(en='1')ELSE'Z';b<=y;ENDone;8.4三態(tài)邏輯設(shè)計(jì)例8.19三態(tài)雙向總線緩沖器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYttl245ISPORT(a,b:INOUTSTD_LOGIC_VECTOR(7DOWNTO0); oe,dir:INSTD_LOGIC); --使能信號(hào)和方向控制ENDttl245;ARCHITECTUREoneOFttl245ISBEGINa<=bWHEN(oe='0'ANDdir='0')ELSE(OTHERS=>'Z');b<=aWHEN(oe='0'ANDdir='1')ELSE(OTHERS=>'Z');ENDone;8.5分頻器設(shè)計(jì)8.5.1占空比為50%的奇數(shù)分頻8.5.2半整數(shù)分頻8.5.3數(shù)控分頻器例8.20占空比為50%的奇數(shù)分頻電路。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.NUMERIC_STD.ALL;ENTITYfdivnISGENERIC(w:INTEGER:=7); --定義類屬參量wPORT(clk,reset:INSTD_LOGIC;clkout:OUTSTD_LOGIC);--輸出時(shí)鐘END;ARCHITECTUREbehavOFfdivnISSIGNALclkout1,clkout2:STD_LOGIC;SIGNALcount1,count2:UNSIGNED(3DOWNTO0);BEGINPROCESS(clk) --計(jì)數(shù)器1BEGIN8.5.1占空比為50%的奇數(shù)分頻例8.20占空比為50%的奇數(shù)分頻電路。

IF(clk'eventANDclk='1')THEN--上升沿觸發(fā)IF(reset='1')THENcount1<="0000";ELSEIF(count1=w-1)THENcount1<="0000";ELSEcount1<=count1+1;ENDIF;IF(count1<(w-1)/2)THENclkout1<='1';ELSEclkout1<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;例8.20占空比為50%的奇數(shù)分頻電路。PROCESS(clk) --計(jì)數(shù)器2BEGINIF(clk'eventANDclk='0')THEN --下降沿觸發(fā)IF(reset='1')THENcount2<="0000";ELSEIF(count2=w-1)THENcount2<="0000";ELSEcount2<=count2+1;ENDIF;IF(count2<(w-1)/2)THENclkout2<='1';ELSEclkout2<='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;clkout<=clkout1ORclkout2; --相或ENDbehav;例8.21n-0.5半整數(shù)分頻器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.NUMERIC_STD.ALL;ENTITYfdivn_5ISPORT(clkin,clr:INSTD_LOGIC;clkout:BUFFERSTD_LOGIC); --輸出時(shí)鐘END;ARCHITECTUREoneOFfdivn_5ISconstantn:UNSIGNED(3downto0):="0100"; --分頻預(yù)置數(shù)nSIGNALclk2,clk1:STD_LOGIC;SIGNALcount:UNSIGNED(3DOWNTO0);BEGINclk2<=clkinXORclk1;PROCESS(clk2,clr)BEGIN8.5.2半整數(shù)分頻例8.21n-0.5半整數(shù)分頻器。IF(clr='1')THENcount<="0000";ELSIF(clk2'eventANDclk2='1')THENIF(count=n-1)THEN --模n計(jì)數(shù)count<="0000";clkout<='1';ELSEcount<=count+1;clkout<='0';ENDIF;ENDIF;ENDPROCESS;PROCESS(clkout)BEGINIF(clkout'eventANDclkout='1')THENclk1<=NOTclk1; --輸出時(shí)鐘二分頻ENDIF;ENDPROCESS;ENDone;例8.22數(shù)控分頻器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.NUMERIC_STD.ALL;ENTITYpdivISPORT(clk:INSTD_LOGIC;d:INUNSIGNED(7DOWNTO0);qout:OUTSTD_LOGIC);END;ARCHITECTUREoneOFpdivISSIGNALfull:STD_LOGIC;BEGINPROCESS(clk)VARIABLEcnt1:UNSIGNED(7DOWNTO0);BEGIN8.5.3數(shù)控分頻器例8.22數(shù)控分頻器。IFclk'EVENTANDclk='1'THENIFcnt1="11111111"THENcnt1:=d;full<='1';--使溢出標(biāo)志信號(hào)full輸出為高電平ELSEcnt1:=cnt1+1;full<='0';ENDIF;ENDIF;ENDPROCESS;div:PROCESS(full)VARIABLEcnt2:STD_LOGIC;BEGINIFfull'EVENTANDfull='1'THENcnt2:=NOTcnt2;IFcnt2='1'THENqout<='1';ELSEqout<='0';ENDIF;ENDIF;ENDPROCESSdiv;ENDone;數(shù)控分頻器仿真波形圖8.5.3數(shù)控分頻器例8.23帶符號(hào)8位乘法器。LIBRARYIEEE;USEIEEE.numeric_bit.all;ENTITYmult8ISGENERIC(MSB:INTEGER:=8);PORT(clk:INBIT;oper_a,oper_b:INSIGNED(MSB-1DOWNTO0);--被乘數(shù)、乘數(shù)result:OUTSIGNED(2*MSB-1DOWNTO0));--乘操作結(jié)果ENDmult8;ARCHITECTUREoneOFmult8ISSIGNALreg_a,reg_b:SIGNED(MSB-1DOWNTO0);SIGNALacc:SIGNED(2*MSB-1DOWNTO0);--乘法結(jié)果暫存ATTRIBUTEmultstyle:STRING;ATTRIBUTEmultstyleOFacc:SIGNALIS"LOGIC";8.6乘法器設(shè)計(jì)例8.23帶符號(hào)8位乘法器。BEGINacc<=reg_a*reg_b;--用乘法運(yùn)算符實(shí)現(xiàn)乘法PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENreg_a<=oper_a;reg_b<=oper_b;result<=acc;ENDIF;ENDPROCESS;ENDone;注：用ATTRIBUTE屬性來指定乘法器實(shí)現(xiàn)的方式，其優(yōu)先級(jí)要高于綜合軟件設(shè)置的乘法器實(shí)現(xiàn)方式。例8.29用常數(shù)數(shù)組實(shí)現(xiàn)數(shù)據(jù)存儲(chǔ)，讀出的數(shù)據(jù)用LED燈顯示。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYrom_ledISPORT(clk50m:INSTD_LOGIC;data:OUTSTD_LOGIC_VECTOR(9DOWNTO0));END;ARCHITECTUREoneOFrom_ledISSIGNALclk10hz:STD_LOGIC;SIGNALaddress:INTEGERRANGE0TO19;TYPEROM_typeISARRAY(0TO19)OFSTD_LOGIC_VECTOR(9DOWNTO0);CONSTANTmyrom:ROM_type:=(0=>"0000000001",1=>"0000000011",2=>"0000000111",

8.7存儲(chǔ)器設(shè)計(jì)例8.29用常數(shù)數(shù)組實(shí)現(xiàn)數(shù)據(jù)存儲(chǔ)，讀出的數(shù)據(jù)用LED燈顯示。3=>"0000001111",4=>"0000011111",5=>"0000111111",6=>"0001111111",7=>"0011111111",8=>"0111111111",9=>"1111111111",10=>"0111111111",11=>"0011111111",12=>"0001111111",13=>"0000111111",14=>"0000011111",15=>"0000001111",16=>"0000000111",17=>"0000000011",

8.7存儲(chǔ)器設(shè)計(jì)例8.29用常數(shù)數(shù)組實(shí)現(xiàn)數(shù)據(jù)存儲(chǔ)，讀出的數(shù)據(jù)用LED燈顯示。18=>"0000000001",19=>"0000000000");COMPONENTclk_div--clk_div分頻器件聲明GENERIC(FREQ:INTEGER);PORT(clk:INSTD_LOGIC;--輸入時(shí)鐘clr:INSTD_LOGIC;clk_out:BUFFERSTD_LOGIC);--輸出時(shí)鐘ENDCOMPONENT;BEGINdata<=myrom(address);--從ROM中讀出數(shù)據(jù)，未寄存PROCESS(clk10hz)BEGIN例8.29用常數(shù)數(shù)組實(shí)現(xiàn)數(shù)據(jù)存儲(chǔ)，讀出的數(shù)據(jù)用LED燈顯示。IF(clk10hz'EVENTANDclk10hz='1')THENIFaddress=19THENaddress<=0;--時(shí)鐘寄存ELSEaddress<=address+1;ENDIF;ENDIF;ENDPROCESS;i1:clk_div--產(chǎn)生10Hz信號(hào)GENERICMAP(FREQ=>10)PORTMAP(clk=>clk50m,clr=>'1',clk_out=>clk10hz);ENDone;8.7存儲(chǔ)器設(shè)計(jì)例8.30clk_div分頻子模塊。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYclk_divISGENERIC(FREQ:INTEGER:=1000);--FREQ為欲得到的頻率值PORT(clk:INSTD_LOGIC;clr:INSTD_LOGIC;clk_out:BUFFERSTD_LOGIC);ENDclk_div;----------------------------------------------ARCHITECTUREoneOFclk_divISCONSTANTNUM:INTEGER:=50000000/(2*FREQ);--計(jì)算得到分頻比SIGNALcount:INTEGERRANGENUMDOWNTO0;BEGIN8.7存儲(chǔ)器設(shè)計(jì)例8.30clk_div分頻子模塊。PROCESS(clk,clr)BEGINIF(clr='0')THENclk_out<='0';count<=0;ELSIF(clk'EVENTANDclk='1')THENIF(count=NUM-1)THENcount<=0;clk_out<=NOT(clk_out);ELSEcount<=count+1;ENDIF;ENDIF;ENDPROCESS;ENDone;8.7存儲(chǔ)器設(shè)計(jì)將本例完成指定目標(biāo)器件、引腳分配和鎖定，并在DE10-Lite目標(biāo)板上下載驗(yàn)證，目標(biāo)器件為10M50DAF484C7G，引腳分配和鎖定如下。set_location_assignmentPIN_P11-toclk50mset_location_assignmentPIN_B11-todata[9]set_location_assignmentPIN_A11-todata[8]set_location_assignmentPIN_D14-todata[7]set_location_assignmentPIN_E14-todata[6]set_location_assignmentPIN_C13-todata[5]set_location_assignmentPIN_D13-todata[4]set_location_assignmentPIN_B10-todata[3]set_location_assignmentPIN_A10-todata[2]set_location_assignmentPIN_A9-todata[1]set_location_assignmentPIN_A8-todata[0]下載配置文件.sof至FPGA目標(biāo)板，觀察10個(gè)LED燈的顯示效果，以驗(yàn)證ROM數(shù)據(jù)讀取是否正確。8.7存儲(chǔ)器設(shè)計(jì)8.8流水線設(shè)計(jì)流水線設(shè)計(jì)是經(jīng)常用于提高所設(shè)計(jì)系統(tǒng)運(yùn)行速度的一種有效的方法。為了保障數(shù)據(jù)的快速傳輸，必須使系統(tǒng)運(yùn)行在盡可能高的頻率上，但如果某些復(fù)雜邏輯功能的完成需要較長(zhǎng)的延時(shí)，就會(huì)使系統(tǒng)難以運(yùn)行在高的頻率上，在這種情況下，可使用流水線技術(shù)，即在長(zhǎng)延時(shí)的邏輯功能塊中插入觸發(fā)器，使復(fù)雜的邏輯操作分步完成，減小每個(gè)部分的延時(shí)，從而使系統(tǒng)的運(yùn)行頻率得以提高。流水線設(shè)計(jì)的代價(jià)是增加了寄存器邏輯，增加了芯片資源的耗用。流水線操作某個(gè)復(fù)雜邏輯功能的實(shí)現(xiàn)需較長(zhǎng)的延時(shí)，可將其分解為幾個(gè)（如3個(gè)）步驟來實(shí)現(xiàn)，每一步的延時(shí)變小，在各步間加入寄存器，以暫存中間結(jié)果，這樣可大大提高整個(gè)系統(tǒng)的最高工作頻率。流水線操作的示意圖非流水線方式8位全加器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYadder8ISPORT(ina,inb:INSTD_LOGIC_VECTOR(7DOWNTO0);cin,clk:INSTD_LOGIC;sum:OUTSTD_LOGIC_VECTOR(7DOWNTO0);cout:OUTSTD_LOGIC); --進(jìn)位ENDENTITY;ARCHITECTUREoneOFadder8ISSIGNALtempa,tempb:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALtempc:STD_LOGIC;SIGNALtemp:STD_LOGIC_VECTOR(8DOWNTO0);BEGIN非流水線方式8位全加器PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENtempa<=ina;tempb<=inb;tempc<=cin;--操作數(shù)寄存ENDIF;ENDPROCESS;PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENtemp<=('0'&tempa)+tempb+tempc;sum<=temp(7DOWNTO0);cout<=temp(8);ENDIF;ENDPROCESS;ENDone;非流水線方式8位全加器非流水線方式8位加法器的RTL綜合視圖兩級(jí)流水實(shí)現(xiàn)的8位加法器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYadder8_pipe2ISPORT(ina,inb:INSTD_LOGIC_VECTOR(7DOWNTO0);cin,clk:INSTD_LOGIC;sum:OUTSTD_LOGIC_VECTOR(7DOWNTO0);cout:OUTSTD_LOGIC);ENDENTITYadder8_pipe2;ARCHITECTUREoneOFadder8_pipe2ISSIGNALtempa,tempb:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALtempc:STD_LOGIC;SIGNALtemp1,temp2:STD_LOGIC_VECTOR(4DOWNTO0);BEGIN兩級(jí)流水實(shí)現(xiàn)的8位加法器PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENtemp1<=('0'&ina(3DOWNTO0))+inb(3DOWNTO0)+cin;tempc<=temp1(4);tempa<=ina(7DOWNTO4);tempb<=inb(7DOWNTO4);ENDIF;ENDPROCESS;PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENtemp2<=('0'&tempa)+tempb+tempc;sum<=temp2(3DOWNTO0)&temp1(3DOWNTO0);cout<=temp2(4);ENDIF;ENDPROCESS;ENDone;設(shè)計(jì)綜合到不同器件的最高工作頻率用QuartusPrime對(duì)源程序進(jìn)行編譯后，選擇菜單Tools→Advisors→TimingOptimizationAdvisor→ReportFmaxSummary，可以看到，非流水線設(shè)計(jì)允許的最大工作頻率為382.7MHz，而2級(jí)流水線設(shè)計(jì)允許的最大工作頻率為460.62MHz，顯然，流水線設(shè)計(jì)有效地提高了系統(tǒng)的最高運(yùn)行頻率。8.9資源共享設(shè)計(jì)資源共享可用來減少系統(tǒng)所耗用的器件資源，尤其是將一些耗用資源較多的模塊進(jìn)行共享，能有效降低整個(gè)系統(tǒng)耗用的資源。例8.36