1、Moore vs. More-Than-More,Name:談國(guó)強(qiáng) Student Number:M201672247,The main content Moores Law and the tendency of CMOS scaling The main peoblems associated with highly scaled CMOS devices. MTM or others,CMOS Device Scaling Trends,Moores Law: Mentioned by Gorden Moore (one of the founders of Faichild/intel

2、) in a 1965 paper It informally predicts that the processing power of computer chip will double approximately every 18 months It has been followed quite closely up to now However, due to the tyrannical laws of physics, Moores law will one day face its ultimate limits and this scaling will come to a

3、halt,CMOS Device Scaling Trends,Minimum dimension:,Wafer size：,CMOS Device Scaling Trends,CMOS Scaling Limit,Physical limit: Atonic size is the ultimate limit of physical transistors Before reaching atomic size, many quantum-mechanical effect will come it to disturb the operation Equipment limit: Ho

4、w to do lithography to define small geometry Cost of equipment and facility,CMOS Scaling Limit,Process variation: Control of dopant density in the channel leading to device-to-device performance variation Small dimension also magnify the error in device dimension,More than Moore,Predictions that Moo

5、res Law has reached it limits have been heard for years and have proven to be premature. We are now nearing the basic physical limits to CMOS scaling and the continuation of the price elastic growth of the industry cannot continue based on Moores law scaling alone. This will require “More than Moore

6、” through the tighter integration of system level components at the package level. In the past scaling geometries enabled improved performance, less power, smaller size and lower cost. Today scaling alone does not ensure improvement of all four items.,More than Moore,More than Moore,Device: FinFET,多

7、fin的FinFET器件三維結(jié)構(gòu)圖,Device: FinFET,There are a few new process and materials challenges in manufacturing FinFET as summarized below: The dry etching on fins is more stringent due to the 3D structure. As a result of the shape of active fins, the fin channel is preferred to be low-doping for minimizing

8、Vt variations related to random doping fluctuations As the Vt of low-doping channel is mainly set by the work-function of gate electrode, it leads to difficult and costly implementation of multi-Vt. It is hard to prevent dopant diffusion into channel. As the etch-stop liner is known not effective as

9、 stressor for FinFET, the non-merged and recessed fin before S/D epi provides effective stress to fin-channel,Device: Carbon Nanotube FET,Carbon nanotubes represent a new class of semiconductor materials whose electrical properties are more attractive than silicon, particularly for building nanoscal

10、e transistor devices that are a few tens of atoms across. Electrons in carbon transistors can move easier than in silicon-based devices allowing for quicker transport of data. The nanotubes are also ideally shaped for transistors at the atomic scale, an advantage over silicon.,Device: Carbon Nanotube FET,Carbon Nanotube Advantages: Incredible Mobility; High Cut-Off Frequencies; Good processability; Low Schottky barriers; Good band gap tunability.,To sum up: Many new structures are being investigated, and each of them has its advantages a