1、5.2 Boolean Algebra and Logic Circuit布爾代數(shù)與邏輯電路Boolean Algebra 布爾代數(shù)Logic Circuit 邏輯電路Logic Gate 邏輯門mathematical logic數(shù)理邏輯logic variable 邏輯變量logic operation 邏輯運算expression 表達式AND operation 與運算 AND gate 與門function table 真值表，函數(shù)表，功能表 OR operation 或運算 OR gate或門NOT operation 非運算 complement 補碼，反碼Inversion 取

2、反 ，反向 Inverter 反相器De Morgans Theorem 摩根定理identity 恒等式composite operations 復合運算NAND 與非 NOR 或非integrated circuit 集成電路logic flow diagram 邏輯流程圖Flip-Flop（FF） 觸發(fā)器memory characteristic 記憶特性SET 置位 CLEAR 復位symmetrical 對稱的illegal 非法的internal內部的 circuitry 電路, 線路memory element 存儲元件, 記憶元件burglar alarm 防盜報警器deact

3、ivate 使無效，使不活動photocell 光電池 ，光電管illuminate 照明，照亮saturated 飽和的 activate 使動作，使活動synchronous 同步的 sequential 順序的synchronous sequential system 同步時序系統(tǒng)synchronize v.同步 master clock 主時鐘periodic 周期的 pulse 脈沖periodic pulse 周期脈沖square wave 方波 duty cycle 占空比interval 時間間隔，間隔rising edge 上升沿 falling edge 下降沿positi

4、ve-going edge 正向沿negative-going edge 負向沿clocked flip-flop 時鐘觸發(fā)器frequency 頻率 propagation delays 傳播延遲trigger 觸發(fā)waveforms 波形 trigger input 觸發(fā)脈沖輸入control input 控制輸入edge-triggered 邊沿觸發(fā) triangle 三角形Boolean Algebra and Logic Gates The section is concerned with digital system variables that take on only two

5、 values (binary variables). We conventionally denote these values as “0”and”1”,and then use a special set of rules called Boolean algebra to summarize the various ways in which digital variables can be combined. This algebra and much of the notation are adopted directly from mathematical logic. Thus

6、, ”logic variable ”or “l(fā)ogic operation” are commonly used in place of “digital variable” or “digital operation”. Definition of the AND operation: Given two input variables, A and B, and an output variable C, the expression. C=A and B means C=1 if A=1 and B=1otherwise C=0 A circuit that performs the

7、AND operation is called an AND gate. The logic symbol for a two-input AND gate is shown in Figure 5.3.A dot is used as a shorthand for the AND operation, so that Eq.5.2 may be written C=A B, the dot is often omitted simplifying further C=AB.布爾代數(shù)和邏輯門        

8、60; 本節(jié)是有關數(shù)字系統(tǒng)的變量就只有兩個值（二進制變量）。我們傳統(tǒng)上表示為“0”和“1”這些值，然后使用一組特殊的規(guī)則稱為布爾代數(shù)，總結在其中數(shù)字變量可以組合各種方法。這個代數(shù)和符號多采用直接從數(shù)理邏輯。因此，“邏輯變量”或“邏輯運算”是常在“數(shù)字變量”或“數(shù)字經(jīng)營”代替。的定義及操作：給定兩個輸入變量，A和B和一個輸出變量C的表達。  ç = A和B指ç = 1如果A = 1和B = 1否則C = 0的  一個電路，執(zhí)行和操作被稱為與門。對于一個二輸入與門，如圖5.3所示的邏輯符號。一個點是作為與操作使用速記，使Eq.5

9、.2可以寫作C = AB，點往往省略進一步簡化ç = AB。One nice feature of digital operations is that the complete set of input output variable values can be written down. Figure 5.3(a)shows such a function table, corresponding to equation C=AB, which lists all possible combinations of input variables A and B together

10、with the corresponding output variable C. From this function table we see that in algebraic terms the AND operation is a form of multiplication, with these manipulation rules: Definition of the OR operation: Given two input D and E, and an output variable F, the expression F=D OR EMeans F=1 if D=1 o

11、r E=1 or both D=1 and E=1The +sign is used as a shorthand for OR, and is never omitted in algebraic expressions, Thus, Eq.5.5 is written algebraically as F=D+EFigure 5.3(b) shows the logic symbol used for the two-input OR gate together with the corresponding function table. Algebraically, the OR ope

12、ration is a special form of addition performed according to these rules:Note that the last manipulation, 1+1=1,differs from the ordinary arithmetic use of the +sign.As in ordinary algebra, parentheses may be used in boolean expressions to group terms and give precedence to operations. If these are n

13、o parentheses, the AND functions in an equation are evaluated first.一個不錯的數(shù)字業(yè)務的特點是，輸入輸出變量值的完整集合可以寫下來。圖5.3（a）顯示這樣的函數(shù)表，相應的方程C = AB公司，其中列出了從這個功能表輸入變量A和B共同所有可能的組合對應的輸出變量與正我們看到，在代數(shù)方面的AND運算是一個乘法的形式，這些操作規(guī)則：的定義或操作：由于D和E兩個輸入和輸出變量樓的表達式F = D或E指女= 1如果D或E = 1 = 1或兩個，均為D = 1和E = 1+號是用作或速記，并永遠不會忽略的代數(shù)表達式，因此，Eq.5.5寫為

14、F = D的代數(shù)+ é圖5.3（b）所示的邏輯符號的雙輸入或門連同相應的功能表中使用。代數(shù)，或操作的是一種特殊形式進行除依照本規(guī)則：注意最后的操縱，1 +1 = 1，從普通的算術+符號使用不同。由于在普通代數(shù)，括號可用于布爾表達式組方面，給予優(yōu)先考慮操作。如果這些是沒有括號，在方程和函數(shù)首先計算。Definition of the NOT operation: In some situations, the opposite value of a particular variable is required. In Boolean algebra, the opposite val

15、ue of a variable is called the complement of that variable, and is denoted by a bar drawn over the variable in question. The complement operation is summarized below using variable G as an example .The logic operation that produces the complement is called inversion, or the NOT operation. The logic

16、symbol and function table for an inverter is shown is Figure 5.3(c). De Morgans Theorem. De Morgans theorem is a Boolean algebra identity expression that states or equivalently(Note that the complete algebraic expression underneath the complement bar must first be evaluated, then the complement take

17、n.) This theorem is easily verified by examining the function tables for the two sides of each equation. NOT運算的定義：在某些情況下，對面的一個特定變量的值是必需的。在布爾代數(shù)中，一個變量的相對值稱為該變量的補充，并得到了有關變量繪制一個酒吧表示。補操作總結如下使用為例變量克。在邏輯運算，從而產生補充被稱為反轉，或不操作。其中的邏輯符號和一個逆變器的功能表顯示的是圖5.3（c）項。       德摩根定理。德摩根定理是

18、一個布爾表達式，代數(shù)身份    國家   或等價（注意：完成下面的補充欄必須先進行評估，然后采取補代數(shù)表達式。）這個定理是很容易通過檢查每個方程為雙方的函數(shù)表核實。In summary, De Morgans theorem states that the complement of the OR operation is equivalent to performing the AND operation on the complement variables, and vice versa. De Morgans the

19、orem is of great use in manipulating and simplifying Boolean algebraic expression that contain more than one basic logic operation .The composite operations NAND and NOR. Two combinations of basic operations arise so often that they are given individual names and logic symbols. The NOR operation is

20、the complement of the OR operation (the name is simply a contraction of “NOT OR”), and is defined by or , by De Morgans theorem,總之，德摩根定理指出的補等于或操作上執(zhí)行的補充變量和操作，反之亦然。德摩根定理是在大量使用，簡化操作布爾代數(shù)表達式包含多個基本的邏輯運算。該復合操作的NAND和NOR。兩個基本操作的組合出現(xiàn)，常常使他們獲得個人姓名和邏輯符號。在NOR型經(jīng)營是補充的或運算（名稱只是一個“不或”）收縮，定義為  或由德摩根定理，Two equ

21、ivalent symbols for the NOR gate, representing Eq.5.9 and Eq5.10 respectively, are shown in Figure5.4(a) along with the NOR function table. Note that the small circle adjacent to the input or output of the basic gate symbols produces the INVERSION of the variable in each case.The complement of the A

22、ND operation is called the NAND operation (from “NOT AND”), and is defined by the two equivalent forms or The two equivalent symbols for NAND gates and the function table are shown in Figure 5.4(b).兩個等價符號或非門，分別代表Eq.5.9和Eq5.10，載于Figure5.4（1）隨著NOR型函數(shù)表。請注意，小圓圈旁輸入或輸出生產基本門符號在每個案件中的變量反演。的補，操作所謂的NAND操作（從“不

23、和”），是由兩個等價形式定義 或  這兩個非門和函數(shù)表相當于符號如圖5.4（b）項。The principal importance of NOR and NAND is that they are the simplest logic functions to construct in integrated circuit form. Thus, while it may be easier for the beginner to learn to “think” with OR and AND , he should also practice thinkin

24、g with NOR and NAND as these functions are likely to be used in the final circuit realization. Also, it is possible to synthesize all of the logic functions using only NOR gates or only NAND gates . Let us formulate a simple everyday situation in terms of digital variables and Boolean operations. Su

25、ppose you are driving home and become thirsty for a hot drink. You see a diner ahead and pull in . Let us develop a Boolean equation for whether or not you obtain a drink. The first step is to assign variables for the problem: The diner is open for business => D=1, or simple D (=>means implies

26、)The diner sells coffee =>CThe diner sells tea =>TYou get a drink =>XThe next step is to use AND and OR operations to construct this Boolean equation: Or omitting the dot Which is equivalent to 主要重要性的NOR和NAND是他們最簡單的邏輯功能，構建在集成電路形式。因此，雖然它可能會更容易為初學者學習“思考的OR和AND”，他也應該實踐的NOR和NAND的思想，因為這些功能可能會在最終

27、電路實現(xiàn)使用。此外，它可以合成的或非門的邏輯只使用或只與非門的所有功能。讓我們在制訂數(shù)字變量和布爾操作方面簡單的日常生活情況。假設你是開車回家，并為熱飲成為渴。您看到一個小餐館前面拉英寸讓我們制定一個你是否取得喝布爾方程。第一步是分配的問題變量： 該餐館是開業(yè) =>“Ð = 1，或簡單Ð（=>”手段暗示）該餐館出售的咖啡=>“ç銷售茶葉的晚餐=>“你去喝點水=>“X下一步是使用AND和OR操作興建此布爾方程：或省略點這相當于The final step is to construct a logic flow di

28、agram using gate symbols. Two possible logic flow diagrams, corresponding to Eq.5.16 and Eq.5.17 are shown in Figure 5.5. As an illustration of how only NOR gates or only NAND gates can be used to synthesize any function, two additional implementation of this same example are shown in Figure 5.6, No

29、tice that when both inputs of the two-input NOR gate are connected together ,as in Figure 5.6(a), the gate becomes an inverter.Flip-Flop from Logic Gates The flip-flop (abbreviated FF) is a logic circuit with two outputs, which are the inverse of each other, which outputs as Q and . The Q output is

30、called the normal FF output and is the inverted FF output. When a FF is said to be in the high (1)state or the low(0) state, this is the condition at the Q output. Of course, the output is always the inverse of Q .There are two possible operating states for the FF: (a) Q=0, =1; and (b) Q=1, =0. The

31、FF has one or more inputs, which are tied to cause the FF to switch back and forth between these two states. As we shall see, once an input signal causes a FF to go to a given state, the FF will remain in that state even after that input signal is terminated. This is its memory characteristic. A bas

32、ic FF circuit can be constructed from two NOR gates connected as shown in the Figure 5.7. Notice that the output of NOR-1 serves as one of the inputs to NOR-2, and vice versa. The two output are Q and , which are always the inverse of one another during normal operation. The two inputs are labeled S

33、ET and CLEAR, for reasons that will soon apparent.最后一步是建立一個邏輯流程圖用門符號。兩個可能的邏輯流程圖，對應Eq.5.16和Eq.5.17如圖5.5所示。作為一個如何的NOR閘或只與非門可以用來合成任何職能畫像，這兩個同樣的例子額外implementation見圖5.6，Notice，當了二輸入或非門兩個輸入連接在一起，作為在圖5.6（a）條，門成為一個逆變器。觸發(fā)器的邏輯門 觸發(fā)器（簡稱法郎）是一個具有兩個輸出，這是對方，作為Q輸出和反邏輯電路。所謂的Q輸出是正常的法郎輸出，倒法郎輸出。當FF是說是在高（1）國家或低（0）狀態(tài)

34、，這是在Q輸出條件。當然，輸出始終是Q的逆。有兩個可能的運行狀態(tài)的FF：（1）問= 0 = 1;及（b）問= 1，= 0。該法郎有一個或多個輸入，這是導致掛鉤FF到這兩種狀態(tài)之間進行切換來回。正如我們將會看到，一旦輸入信號導致法郎到一個給定的狀態(tài)，法郎將在該州仍然即使該輸入信號被終止。這是它的記憶特性。一個基本的電路可以法郎建造，在香港如圖5.7所示連接兩個或非門。請注意的NOR - 1的輸出作為輸入1的NOR - 2，反之亦然。兩個輸出是Q和，總是一個在正常運作另一個逆。這兩個輸入標記設置和清除，原因是什么將很快顯現(xiàn)。Let us begin our analysis of the NOR

35、FF circuit by making both inputs low (SET=CLEAR=0). In this situation we cannot determine what the Q and output values are since there are two, equally likely, possibilities: (a) Q=0, =1, and (b) Q=1, =0. To verify this, let us first assume that Q is 0. This 0 and the 0 from the SET input produce a

36、1 at the NOR-1 output, thereby making Q=1(recall that a NOR output is 1 only when all its inputs are 0). This Q=1 is fed to the NOR-2 input, thereby producing a 0 at its output; so Q=0, as was originally assumed.Now, let us assume instead that Q=1.This 1 applied to NOR-1produce a 0 at its output, so

37、 Q=0. The Q=0 is fed to NOR-2 together with the 0 from the CLEAR input, thereby producing a 1 at its output; so Q=1,as was originally assumed.Thus, with SET and CLEAR both 0, the FF outputs can be in either state. Actually, the FF output state will depend on what has previously occurred at the input

38、s. The SET=CLEAR=0 condition will not affect the FF outputs; they will simply remain in whatever state they happen to be in at the time. This is the first case shown in the table and represents the “normal” state. In other words, the SET and CLEAR inputs are normally in the 0 state.To make the FF go

39、 to a specific state, we must put a 1 on the appropriate input. To make Q=1, we must apply a 1 to the SET while keeping CLEAR=0. The 1 at the SET input causes NOR-1 to go 0, so Q=0. This 0 fed to NOR-2 along with CLEAR=0 causes NOR-2 to produce Q=1. 讓我們開始制作都投入低（集=清除= 0），我們的NOR電路分析法郎。在這種情況下，我們不能確定什么Q

40、和輸出值，是因為有兩個，同樣有可能，可能性：（1）問= 0，= 1，（二）問= 1，= 0。為了驗證這一點，讓我們先假設Q為0。這從0 SET輸入0出示了NOR - 1輸出為1，從而為Q = 1（記得，輸出為1的NOR只有當所有的輸入0）。這是美聯(lián)儲為Q = 1到了NOR - 2的投入，從而在輸出端產生一個0，所以為Q = 0，如最初設想。 現(xiàn)在，讓我們假設，而不是使Q = 1，本一適用于NOR型1produce在其輸出為0，所以為Q = 0。在Q = 0是美聯(lián)儲的NOR - 2一起從CLEAR輸入0，從而產生在其輸出為1，所以為Q = 1，原來承擔。 因此，在設置和清除均為0，整個FF輸出可

41、以在任何一國。其實，法郎輸出狀態(tài)將取決于我們在以前發(fā)生的投入。在SET =清除= 0的條件，不會影響法郎產出，他們會簡單地停留在任何國家，他們將在發(fā)生時間較長。這是第一例在表中顯示，代表了“正常”狀態(tài)。換句話說，輸入的設置和清除，通常在0的狀態(tài)。 為了使法郎轉到一個特定的國家，我們必須放在適當?shù)耐度霝?。為了使為Q = 1，我們必須申請1至設定的同時保持清除= 0。 1在設定輸入導致的NOR - 1去0，所以為Q = 0。這0美聯(lián)儲的NOR - 2 = 0清除沿著原因的NOR - 2生產為Q = 1。 Thus, a 1 on the SET input (while CLEAR=0) wil

42、l always produce Q=1( =0). This 1 need only be present long enough to allow the gates to respond and pass the signal. When SET returns to 0, so that both inputs are 0,the FF will remain in the Q=1 state. This is the second case listed in the table.Clearly, since the circuit is completely symmetrical

43、, it can be seen that a 1 applied to the CLEAR input while SET=0 will produce a FF output state of Q=0( =1). When the CLEAR input returns to 0, the FF will remain in the Q=0 state. This is the third case listed in the table.The last case to consider is SET=CLEAR=1,This condition will produce 0 at th

44、e output of both NOR gates, so Q=0 and =0. This is obviously an illegal condition if it is desired that the FF outputs be the inverse of each other. Furthermore, when the inputs are returned to 0, the FF output state will depend on which input reaches 0 first. This makes the SET=CLEAR=1 condition am

45、biguous. For these reasons the latter case is never purposely used during the operation of this type of FF.因此，1對SET輸入（同時清除= 0）將始終產生為Q = 1（= 0）。這1只需要足夠長的時間，使目前的大門作出回應，并通過信號。當SET返回為0，這兩個輸入是0的話，將繼續(xù)留在了FF的Q = 1的狀態(tài)。這是第二種情況表中列出。顯然，由于電路完全對稱的，可以看到，一個1適用于有明確的輸入，同時集= 0將產生一個輸出狀態(tài)的Q法郎= 0（= 1）。當CLEAR輸入返回為0，將繼續(xù)留在法郎

46、的Q = 0的狀態(tài)。這是第三種情況表中列出。最后一種情況下要考慮的是集=清除= 1，這種情況會產生在兩個或非門輸出0，所以Q二0       = 0。這顯然是非法的條件，如果它是理想的法郎產出是相互逆。此外，當輸入返回到0時，輸出狀態(tài)法郎將取決于它輸入到0首。這使得在SET =清除= 1條件含糊不清?；谶@些原因，后一種情況下是沒有特意在這次的FF式操作使用。The SET-CLEAR(S-C) Flip-Flop The FF circuits described above are examples of SET-CLE

47、AR (S-C) flip-flops. The general logic symbols used to represent the S-C FF are shown in the Figure5.8 with their corresponding truth tables. The figure (a) represents the S-C FF that responds to high levels on its S and C inputs, such as the NOR-gate FF. And the Figure (b) represents the S-C FF tha

48、t responds to low levels on its S and C inputs, such as the NAND-gate FF. Note the small circles shown on the S and C inputs to indicate that this FF responds to 0s on these inputs. We shall generally use these block symbols to represent S-C FFs instead of showing the complete internal circuitry. Th

49、e S-C flip-flop forms the basis for many other types of flip-flop circuits. By itself the S-C FF is useful as a memory element to store information. To illustrate, the Figure 5.9 shows a simple burglar alarm circuit using a S-C FF.The FF is initially in the Q=0 state, so the alarm is deactivated. Wi

50、th the photocell illuminated, the transistor is saturated, so Vx=0, applying a low to the S input. If the photocell goes dark, the transistor is turned off and Vx=5V, This applies a high to the S input, causing the FF to go to the Q=1 state, thereby activating the alarm. The FF, once it has been set

51、 to Q=1, will stay there (acts memory) even if the photocell immediately goes light again. Thus, the alarm will persist until the FF is cleared to the Q=0 state by applying a momentary 1 to the C input. 在設置清除（第S -丙）觸發(fā)器    上述電路的法郎，是集清晰（SC）的觸發(fā)器的例子。一般的邏輯符號來表示的SC法郎是在與其相應的真值表Figure5.8所示。這個

52、數(shù)字（1）代表資深大律師法郎，響應其S和C的高層次，如或非門法郎投入。 而圖（二）代表資深大律師法郎，響應其S和C水平低，如與非門法郎的投入。注意：顯示在S和C的投入，這表明法郎回應0年代就這些投入的小圓圈。一般我們會使用這些符號來代表資深大律師塊農民田間學校，而不是顯示了完整的內部電路。 常設委員會觸發(fā)器構成的觸發(fā)器電路，許多其他類型的基礎。通過自身的SC FF是有用的作為一個存儲單元來存儲信息。為了說明這一點，圖5.9顯示了一個簡單的防盜報警器電路使用一個資深大律師法郎。 在最初的法郎的Q = 0的狀態(tài)，所以報警停用。隨著光電照明，晶體管飽和，所以Vx的= 0，采用低到S輸入。如果光電熄滅

53、，晶體管處于關閉狀態(tài)和VX = 5V時，這適用于高的S輸入，導致法郎去到Q = 1的狀態(tài)，從而激活了警鐘。該法郎，一旦它被設置到Q = 1，將呆在那里（行為內存），即使光線的光電池立即去了。因此，警報將持續(xù)到法郎被清除到Q采用一時一到C = 0的輸入狀態(tài)。 The Clocked S-C Flip-FlopMost digital systems operate as synchronous sequential systems. What this means is that the sequence of operations that takes place is synchronize

54、d by a master clock signal, which generates periodic pulses that are distributed to all parts of the system. This clock signal is usually one of the forms shown in the following Figure 5.10, very often it is a square wave (50 per cent duty cycle), such as the one shown in the figure (b).The clock si

55、gnal is the signal that causes things to happen at regularly spaced intervals. In particular, operations in the system are made to take place at times when the clock signal is making a transition from 0 to 1 or from 1 to 0. These transition times are pointed out in the figure. The 0-to-1 transition

56、is called the rising edge or positive-going edge of the clock signal; the 1-to-0 transition is called the falling edge or negative-going edge of the clock signal. The synchronizing action of the clock signal is the result of using clocked flip-flop, which are designed to change states on either (but

57、 not both) the rising edge or the falling edge of the clock signal. In other words, the clocked FFs will change states at the appropriate clock transition and will rest between successive clock pulses. The frequency of the clock pulses is generally determined by how long it takes the FFs and gates i

58、n the circuit to respond to the level changes initiated by the clock pulse, that is, the propagation delays of the various logic circuits.該時鐘的S - ç觸發(fā)器 大多數(shù)數(shù)字系統(tǒng)同步連續(xù)運作系統(tǒng)。這意味著該業(yè)務發(fā)生的順序是由主時鐘信號，產生的是分配給該系統(tǒng)的所有部件周期脈沖同步。這個時鐘信號通常是在以下圖5.10，很多時候它是一個方波占空比百分之五十（）所示的形式，如在圖（所示的，一架B）。 該時鐘信號是信號，導致事情發(fā)生在定期間隔時間。尤其是，業(yè)務系統(tǒng)是由以發(fā)生時間時，時鐘信號正在從0到1或1到0的過渡。這些過渡時期，指出了在圖中。 0比1的過渡稱為上升沿或正持續(xù)在時鐘信號邊緣的1到0的過渡稱為下降沿或負向的時鐘信號邊沿。 在時鐘信號同步行動是使用頻率觸發(fā)器，其目的是為了改變國家的結果是（但不能同時）的上升沿或下降沿的時鐘信號。換句話說，農民田間學校的時鐘將在適當?shù)母淖儠r鐘過渡態(tài)和休息之間將連續(xù)時鐘脈沖。 在時鐘脈沖的頻率一般是確定需要多久才能在農民田間學校和門電路的響應水平變化的時鐘脈沖啟動，即在各種邏輯電路的傳輸延遲。The above Figu