M/BDesignBasicsDWHD-PCA-EE:Tune第一頁，共二十七頁。RoadmapM/BBlockDiagramsM/Bbasiccomponents–R/L/CM/Bbasiccomponents–ChipsetM/Bbasiccomponents–SuperI/OM/Bbasiccomponents–CPUPCIEIntroduction8B/10BCoding第二頁，共二十七頁。M/BBlockDiagramsFSBDMIDDR2channelAVGA/DVI/HDMIPCIEX16USB2.0(12Ports)SATAIIinterfaceDDR2channelBPCIinterfaceComPortPrinterPortPS/2PortFloppyPortHDAudioNetworkPHYI/FPCIEX1interface第三頁，共二十七頁。M/BBlockDiagrams–ActualM/B第四頁，共二十七頁。M/Bbasiccomponents–RResistorspecificationPowerRating:(ratedpower@70degree)RC04021/16WRC06031/10WRC08051/8WRC12061/4WRatedVoltage:theDCorAC(rms)continuousworkingvoltagecorrespondingtotheratedpowerisdeterminedbythefollowingformula.ElectricalcharacteristicoperatingtemprangemaximumworkingvoltageMaximumoverloadvoltageDielectricwithstandingvoltageResistancerangeTempcoefficientResistorapplicationonmotherboardJumperforreserveddesignordebug,often0resistor;PulluporpulldowntosomelogiclevelImpedancematchforclockandhighspeedsignalForpower,usedasdampingresistor,powerbleedoff第五頁，共二十七頁。M/Bbasiccomponents–C[SMD]CapacitorspecificationSize:RC0402RC0603RC0805RC1206RatedVoltage:10V,16V,25V,50VElectricalfeatures:operatingtemprangeCapacitancetoleranceoperatingtemperatureLoadlifecasesizecapacitorapplicationonmotherboardPowerdecouplingtostabilizeasignalorpowerrailEMIsignalsink,100pF,150pF…RCdelay,suchas100nF,1uF…Highspeedsignalcoupling,suchas100nFTolerance:NPOX5RX7RY5VM5U第六頁，共二十七頁。M/Bbasiccomponents–C[PTH]CapacitorspecificationParameter:CapacitanceESR,DissipationFactorImpedanceLeakagecurrentElectricalcharacteristicoperatingtemprangemaximumworkingvoltageMaximumoverloadvoltageDielectricwithstandingvoltageResistancerangeTempcoefficientE-CapacitorapplicationonmotherboardPowerdecoupling,tostabilizepowerrailAudioSignalcouplingLowESRcap,forripplecurrentfilterTolerance:AlECAPOS-CONFPCAP第七頁，共二十七頁。M/Bbasiccomponents–L[SMD]CapacitorspecificationType:Chipinductor–SignalThinFilmChipInductorMultilayerChipInductorWireWoundChipInductorFerritebead-EMIDifferentialmodeCommonmodePowerInductorElectricalcharacteristicoperatingtemprangemaximumworkingvoltageMaximumoverloadvoltageDielectricwithstandingvoltageResistancerangeTempcoefficientChipinductorapplicationonmotherboardDepressthenoiseintopowerSignalprocess,impedancematchasasignalfiltersuchaspowerandVGAsignalasEMIfilter.USBsignal,commonmodenoisedepressForpowerprocessTolerance:5%,10%20%,25%第八頁，共二十七頁。M/Bbasiccomponents–L[DIP]ChokespecificationProcess:IRONCoilPMCParameter:L:inductancevalueRDC:internalDCresistorIDC:ratingcurrentQ:TestFrequencyworkingtemperature resonantfrequencyElectricalcharacteristicoperatingtemprangemaximumworkingvoltageMaximumoverloadvoltageDielectricwithstandingvoltageResistancerangeTempcoefficientchokeapplicationonmotherboardPowerprocess,DC-DCpoweroutputchokeEMIfilter,DC-DCpowerinputchoke第九頁，共二十七頁。M/Bbasiccomponents–chipsetGMCHHostInterface:FSBGTLClockGraphicsI/FVGADVI/HDMIPCIEX16DMIInterfaceDMILINKMemoryInterfaceDDRIIDDRIIIMaximum8GBDualChannel,4-DIMMNBfunctiononmotherboardHostinterfacetoCPU,andmakeabridgebetweentheICH,Memory,GraphicsandCPU.Integratedcore:PCI/PCIEbridge,Memorycontroller,AGP,PCIE/PCItoHostbridgeNBcapability:Graphicsprocess:tosupporttheDirectX9.0,10.0…renderingtechnologyDisplay/MediaContent:HDMI/DVI/DisplayPort,HD-DVD,Blue-RayMemoryspeed:tomatchwithmemorytypeorspeedFSBspeed:tomatchwithCPUFSB第十頁，共二十七頁。M/Bbasiccomponents–chipsetICHHostInterface:DMItoGMCHpoint–to-pointlinkStorageSATAII3Gb/sRAIDNetworkInterfaceLCI/GLCIEthernetPHYUSB2.0Interface12Ports6UHCI2EHCIUSBlegacysupportExpandSlotPCIRev2.3,3SlotsPCIEX1,6SlotsSBfunctiononmotherboardHostinterfacetoNB,andmakeabridgebetweentheSIO,PCI,PCIE,andNB.Integratedcore:PCI/PCIEbridge,PIDE/SATAcontroller,AudioLink,NetworkPHY,legacycore:RTC,interruptcontroller,SMbuscontroller,APICcontrollerNBcapability:Storage:tosupporttheDirectX9.0,10.0…renderingtechnologyExpandability:supportPCI,PCIEnumbersNetwork:EthernetPHY AudioLink:AC’97,HDAAudioInterfaceHADLink第十一頁，共二十七頁。M/Bbasiccomponents–SuperI/OLPCInterface:connecttoSBmulti-drop,similartoPCIStorageFloppyCOMPortModemserialportKeyboardserialcommunicationPrinterPortLegacyprinterportPS/2KeyboardMouseSIOfunctiononmotherboardToprovidethecommunicationpathforlegacydevicetoICHIntegratedlegacycore:UART,Floppycontroller,Printercontroller,PS/2controller,第十二頁，共二十七頁。M/Bbasiccomponents–CPUDesktopProcessorPerformance/Features:?coresnumbers?on-chipSharedCacheSize?SimultaneousMulti-Threadingcapability(SMT)?FSB/QPI?NewinstructionsPower:?65W,95W,130WFMBSocket:mPGA478LGA775socketLGA1336socketProcessTechnology:130nm,Prescott90nm,65nm,Conroe45nm,wolfdale第十三頁，共二十七頁。M/Bbasiccomponents–CPUexampleDesktopBloomfieldProcessorPerformance/Features:?4cores?8Mon-chipSharedCache?SimultaneousMulti-Threadingcapability(SMT)?Intel?QuickPathInterconnect(QPI)?IntegratedMemoryController(IMC)?NewinstructionsPower:?130WFMBSchedule?Q1’08Firstsamples?Q4’08LaunchHEDTSocket:?NewLGA1336SocketProcessorTechnology:?45nmCPU第十四頁，共二十七頁。M/Bbasiccomponents–CPUTrendDesktopProcessornewtechnologyFastRadix-16DividerFasterOSPrimitiveSupportEnhancedIntelVirtualizationTechnology

LargerCaches:upto12MB24WaySetAssociativelyIntel?WideDynamicExecutionIntel?AdvancedSmartCache

SplitLoadCacheEnhancementImprovedStoreForwardingHigherbusspeeds

Intel?SSE4instructionsSuperShuffleEngineDeepPowerDownTechnologyEnhancedIntelDynamicAccelerationTechIntel?SmartMemoryAccessIntel?AdvancedDigitalMediaBoostIntel?IntelligentPowerCapabilityIntelCoreMicroarchitectureNewwiththePenrynFamily第十五頁，共二十七頁。PCIEIntroduction-KeyAttributesScalableWidth,FrequencyHigherBandwidthConsolidatetheI/OUnifyproliferatedsegmentsWorksinexistingPCIEnvironmentHighPerformanceI/OSimplificationLayeredArchitecture=>longevityReliability,Availability,ServiceabilityAdvancedPowerManagementVirtualChannelsQualityofService/IsochronesNewFormFactors/InnovativeDesignsHotPlug/HotSwapAdvancedArchitectureNextGen3D/MultimediaEaseofUse第十六頁，共二十七頁。PCIEIntroduction-ArchitectureRe-use:IPHouses,Foundries,ToolVendors,RTLComputeIndustrywork:Verification,Interoperability,DesignCollateral,MassiveEconomiesofScale&InvestmentsPCIExpressTargetsChip-to-ChipAdvancedSwitchingTargetsFabricsPCIPnPModelinit,enum,configASFabricMngmtinit,enum,configPCISoftwareDriverModelPEIPEIPEIPhysicalLayerLinkLayerTransactionLayerLayer4+MarketSegmentOptimizationsL1/L2Commonality第十七頁，共二十七頁。PCIEIntroduction-TransactionLayerInitializationandconfigurationPacketgenerationandprocessserviceFlowcontrolserviceOrderingrulesSplitTransaction

Postedandnon-postedrequestsnon-postedrequestrequirecompletionsTransactionTypes

Memory,I/O,Configuration,MessageHeaderDate第十八頁，共二十七頁。PCIEIntroduction-DataLinkLayerLinkManagementinitializationandpowermanagementDataintegrityDataprotection,errorchecking,andretryservicesTLPsequencenumberDataProtectionCodeHeaderDateSeq.#CRC第十九頁，共二十七頁。PCIEIntroduction-PhysicalLayerInitializationandconfigurationPacketgenerationandprocessserviceFlowcontrolserviceOrderingrulesHeaderDateSeq.#CRCFramingFraming第二十頁，共二十七頁。PCIEIntroduction-Definitions第二十一頁，共二十七頁。8B/10BCoding-Part1History/applicationThecodewasdescribedin1983byAlWidmerandPeterFranaszekintheIBMJournalofResearchandDevelopment.IBMwasissuedapatentfortheschemethefollowingyear.IBM'spatentnotwithstanding,themethod,implementationandgoalsareverysimilartoGroupCodeRecording(GCR)usedonfloppydisksinsomecomputersduringlate1970s/early80sHistoryApplicationPCIExpressIEEE1394bSerialATASASFiberChannelSSA

HyperTransportInfiniBand

XAUISerialRapidIODVI(TransitionMinimizedDifferentialSignaling)DVBAsynchronousSerialInterface(ASI)GigabitEthernet(exceptforthetwistedpairbased1000Base-T)第二十二頁，共二十七頁。8B/10BCoding-Part2HowitworksHowitworksAstheschemenamesuggests,8bitsofdataaretransmittedasa10-bitentitycalledasymbol,orcharacter.Thelow5bitsofdataareencodedintoa6-bitgroupandthetop3bitsareencodedintoa4-bitgroup.Thesecodegroupsareconcatenatedtogethertoformthe10-bitsymbolthatistransmittedonthewire.Because8b/10bencodinguses10-bitsymbolstoencode8-bitwords,someofthepossible1024codescanbeexcludedtograntarun-lengthlimitof5consecutiveequalbitsandgrantthatthedifferenceofthecountof0sand1sisnomorethan2.Someofthe256possible8-bitwordscanbeencodedintwodifferentways.Usingthesealternativeencodings,theschemeisabletoaffectlong-termDC-balanceintheserialdatastream.Theencodingisnormallydoneentirelyinhardware.Upperlayersofthesoftwarestackshouldbe"unaware"thatthisencodingisbeingused.第二十三頁，共二十七頁。8B/10BCoding-Part2CodeTableinputRD=-1RD=+1inputRd=-1Rd=+1HGFfghjHGFfghjD.x.000011010100K.x.000010110100D.x.10011001K.x.1200101101001D.x.20100101K.x.2200110100101D.x.301111000011K.x.301111000011D.x.410011010010K.x.410011010010D.x.51011010K.x.5200101011010D.x.61100110K.x.6200110010110D.x.P7111111100001D.x.A7111101111000K.x.A72111011110003B/4BNote1:ForD.x.7,thePrimary(D.x.P7)orAlternate(D.x.A7)encodingmustbeselectedinordertoavoidarunoffiveconsecutive0sor1swhencombinedwiththepreceding5b/6bcode.Sequencesoffiveidenticalbitsareusedincommacodesforsynchronizationissues.D.x.A7isonlyusedforx=17,x=18andx=20whenRD=-1andforx=11,x=13andx=14whenRD=+1.Withx=23,x=27,x=29andx=30,thesamecodeformsthecontrolcodesK.x.7.Anyotherx.A7codecan'tbeusedasitwouldresultinchancesformisalignedcommasequences.Note2:ThealternateencodingfortheK.x.ycodeswithdisparity0allowforK.28.1,K.28.5andK.28.7tobe"comma"codesthatcontainabitsequencethatcan'tbefoundelsewhereinthedatastream第二十四頁，共二十七頁。8B/10BCoding-Part2CodeTable5B/6BinputRD=-1RD=+1HGFEDCBAAbcdeifghjAbcdeifghjK.28.00001110000111101001100001011K.28.10011110000111110011100000110K.28.20101110000111101011100001010K.28.30111110000111100111100001100K.28.41001110000111100101100001101K.28.51011110000111110101100000101K.28.61101110000111101101100001001K.28.71111110000111110001100000111K.23.71111011111101010000001010111K.27.71111101