實(shí)驗(yàn)名稱：補(bǔ)碼乘法器的設(shè)計(jì)與實(shí)現(xiàn)姓名：劉家旭學(xué)號：1414020105一、實(shí)驗(yàn)?zāi)康恼莆斩c(diǎn)小數(shù)補(bǔ)碼乘法運(yùn)算的運(yùn)算方法；理解補(bǔ)碼乘法的運(yùn)算規(guī)則；學(xué)會使用狀態(tài)機(jī)設(shè)計(jì)時序電路；二、實(shí)驗(yàn)內(nèi)容用VHDL編寫一個字長5位的二進(jìn)制定點(diǎn)小數(shù)補(bǔ)碼乘法器。硬件的框圖如下done［框圖如下done［卅…0):8位乘法器H iL A iiresetn 丫(4...0) start汕4…0) clock三、 實(shí)驗(yàn)要求通過對操作性實(shí)驗(yàn)的練習(xí)，自行完成設(shè)計(jì)實(shí)例。熟悉QuartusII的設(shè)計(jì)流程。在實(shí)驗(yàn)報(bào)告中寫出完整的設(shè)計(jì)過程。四、 實(shí)驗(yàn)結(jié)果

好TV%%%￥魚26T268db/1 k<2=1234567g9101112131415161718192Q21222324252627282930313233343536SENTITYmult5ISS PORT(clock,resetnfstart:INstdlogic;x,y:INstdlogic,vector(5DOWNTO1};p:OUTstdlogicvector(9DOWNTO1};done:OUTstdlogicendraultS;ARCHITECTUREexampleOFrmiiiltSISSIGNALry:stdlogicvector(6DOWNTO1};SIGNALpp:stdlogicvector(11DOWNTO0};SIGNALstate:integerRANGE0TO5;BEGINiuiultxply:process(resetnrclock}VARIABLEtemp:stdlogicvector(6DOWNTO1};BEGINIFzesetn=,0,THENry<=(OTHERS=>'01};PP<=(OTHERS^101};state<=0;dem皂C=1□1;ELSIFclock'eventandclock=,l,THENCASEstateISWHEN0=>ry<=y(5)(5DOWNTO1};PP<=rr000000rr&x(5DOWNTO1}^'O1;IFstart=,l?THENstate<=l;ENDIF;WHEN5=>S IFpp(1DOWNTO0}=rr01rrTHENtemp:=pp(11DOWNTO€}+ry;B ELSIFpp(lDOWNTO0}=rr10rrTHENtemp:=pp(11DOWNTO6)+NOTry+1;a ELSE'匚w 1Idlet補(bǔ)碼乘法器-.□MicrosoftEx...勒1314010110.d...超QuartusII.EE316:29開始仿真Stic/新建文件夾/wer.vhd[11E255][01E0][1][255]當(dāng)Files[jPDesignUnits][01WToT★JUIo盞館沁60.040.0HProcessing(17J/CExtraInfo\Info(17)\Warning~CriticalWarning~\Error\Suppressed\Flag/20.0ns?肛蟲険tZLimt壯itmr|'rogi-amDevice(.0penFrogrammer〕FileEditViewProcessingToolsWindow _ =!Groups=盡1 Bl[7]MNamed:~ompileDesignArL：ilysisfttheziEFitterij'lacH?Rijutp)A-EiembleriGenerateprogi-:iiTimingfi1ejGCwer T饋"色◎冷1?羅■臨竜0?OViewProjectAssignments;ProcessingToolsWindowHelpCombinationalALl.lTsII:EP2S15F672C35加26(26)7.45ns+|Pointer:59.0nsInterval:52.35nsStart:|OpsEnd1.0usCompilationReport-FlowSummaryNamer^0clock妙1done矽2國P12resetn?13start?14國x^20□y<ill>MasterTimeBar:NodeName*HE譯Bx[5..1]In|Ax[5]IEA--3<[4]In|—A3<[3]In|Ax[2]InlvNodeNameDirectionLocationI/OBankVREFGroupI/OStandardReserved1AdockInputPIN.D133B3N03.3-VLVTTL(default)2adoneOutputPIN.AA137B7N13.3-VLVTTL(default)3妙p[9]OutputPINY1.28B8N03.3-VLVTTL(default)4妙p[8]OutputPINY：187B7N03.3-VLVTTL(default)5抄p[ZOutputPIN.AA207B7N03.3-VLVTTL(default)6? p[6]OutputPIN.U177B7N03.3-VLVTTL(default)7襯p[5]OutputPIN.U187B7N03.3-VLVTTL(default)8襯p[4]OutputPINV：187B7N03.3-VLVTTL(default)9襯p[3]OutputPIN.W197B7N03.3-VLVTTL(default)10襯p[2]OutputPIN.AF227B7N03.3-VLVTTL(default)11&p[l]OutputPIN.AE227B7N03.3-VLVTTL(default)12?resetnInputPING265B5NO3.3-VLVTTL(default)B?startInputPINN235B5N13.3-VLVTTL(default)14Ax[5]InputPINY137B7N13.3-VLVTTL(default)15Ax[4]InputPINAA147B7N13.3-VLVTTL(default)16Ax[3]InputPINAC217B7NO3.3-VLVTTL(default)17Ax[2]InputPINAD217B7NO3.3-VLVTTL(default)18Ax[l]InputPINAD237B7NO3.3-VLVTTL(default)19Ay[5]InputPINAD227B7NO3.3-VLVTTL(default)20Ay[4]InputPINAC227B7NO3.3-VLVTTL(default)21Ay[3]InputPINAB217B7NO3.3-VLVTTL(default)22Ay[2]InputPINAF237B7NO