11110000000根據(jù)3-8譯的真值表，可得輸出的函數(shù)表達式LD0SW2SW1SW0LD1SW2SW1SW0LD2SW2SW1SW0LD3SW2SW1SW0LD4SW2SW1SW0LD5SW2SW1SW0LD6SW2SW1SWLD7SW2SW1SW圖13-8譯的邏輯電路121ABS000000010101001011101000110110110101111101110SABCiABCiABCiABCoABCiABCiABCi(AB)Ci24位并行進位加法器框圖，本實驗中用Verilog24位并行進位又稱為復用器（Multiplexer）,并用MUX來表示。321選擇控制輸出AB00000100100111010010011110101111211所示，其中，A、B2路數(shù)據(jù)輸入，S為CSA24324五、實驗器材（設(shè)備、元器件PC機、WindowsXP、AnvylNexys3開發(fā)板、XilinxISE14.7DigilentAdept工具六、七、關(guān)鍵源代碼moduleinputSW2,SW1,SW0moduleinputSW2,SW1,SW0outputLD7,LD6,LD5,LD4,LD3,LD2,LD1,not(SW0_L,SW0);not(SW1_L,SW1);not(SW2_L,SW2)and(LD0,SW2_L,SW1_L,SW0_L)and(LD1,SW2_L,SW1_L,SW0)and(LD2,SW2_L,and(LD3,SW2_L,,SW0_L),)and(LD4,SW2and(LD5,SW2and(LD6,SW2and(LD7,,SW1_L,SW0_L),SW1_L,),,,SW0_L),)SW2SW2=0;SW1=0;SW0=0#100;SW0=1#100;SW1=1;SW0=0#100;SW0=1;#100;SW2=1;SW1=0;SW0=0#100;SW0=1;#100;SW1=1;SW0=0#100;SW0=1;圖4譯的仿真結(jié)譯在Anvyl開發(fā)板上的約束文NETSW0LOC=V5;NETSW1LOC=U4;NETSW2LOC=NETLD0LOC=W3;NETLD1LOC=Y4;NETLD2LOC=Y1;NETLD3LOC=Y3;NETLD4LOC=AB4;NETLD5LOC=W1;NETLD6LOC=AB3;NETLD7NETSW0NETSW0LOC=T10;NETSW1LOC=T9;NETSW2LOC=V9;NETLD0LOC=U16;NETLD1LOC=V16;NETLD2LOC=U15;NETLD3LOC=V15;NETLD4LOC=M11;NETLD5LOC=N11;NETLD6LOC=R11;NETLD7LOC=T11;4．4 A3,A2,A1,A0; B3,B2,B1,B0; C0outputC4,S3,S2,S1,S0 g3_L,p3_L,g2_L,p2_L,g1_L,p1_L,go_L,p0_L; c0_L; hs3,c3,hs2,c2,hs1,c1,hs0,c0; (g3_L,A3,B3); (p3_L,A3,B3) (g2_L,A2,B2); (p2_L,A2,B2) (g1_L,A1,B1); (p1_L,A1,B1) (g0_L,A0,B0); (p0_L,A0,B0) (c0_L,C0) (w1,p3_L) (w2,p2_L,g3_L) (w3,p1_L,g3_L,g2_L) (w4,p0_L,g3_L,g2_L,g1_L) (w5,g3_L,g2_L,g1_L,g0_L,c0_L); (C4,w1,w2,w3,w4,w5); (hs3,g3_L,~p3_L); (w6,p2_L); (w7,p1_L,g2_L) (w8,p0_L,g2_L,g1_L) (w9,g2_L,g1_L,g0_L,c0_L); (c3,w6,w7,w8,w9); (S3,hs3,c3) (hs2,g2_L,~p2_L); (w10,p1_L); (w11,p0_L,g1_L) (w12,g1_L,g0_L,c0_L); (c2,w10,w11,w12); (S2,hs2,c2) (hs1,g1_L,~p1_L); (w13,p0_L); (w14,g0_L,c0_L); (c1,w13,w14); (S1,hs1,c1) (hs0,g0_L,~p0_L); (c0,c0_L); (S0,hs0,c0)#100#100C0=#100C0=0;B3=1;B2=1;B1=1;B0=1;#100;A3=1;A2=1;A1=1;A0=1;#100;C0=1;5NETB0NETB0LOC=V5;#SW0NETB1LOC=U4;#SW1NETB2LOC=V3;#SW2NETB3LOC=P4;#SW3NETA0LOC=R4;#SW4NETA1LOC=P6;#SW5NETA2LOC=P5;#SW6NETA3LOC=P8;NETS0LOC=W3;#LD0NETS1LOC=Y4;#LD1NETS2LOC=Y1;#LD2NETS3LOC=Y3;#LD3NETC4LOC=AB4;NetC0Loc=E6;Nexys3NETB0LOC=T10;#SW0NETB1LOC=T9;#SW1NETB2LOC=V9;#SW2NETB3LOC=M8;#SW3NETA0LOC=N8;#SW4NETA1LOC=U8;#SW5NETA2LOC=V8;#SW6NETA3LOC=T5;#SW7NETS0LOC=U16;#LD0NETS1LOC=V16;#LD1NETS2LOC=U15;#LD2NETS3LOC=V15;#LD3NETC4LOC=M11;#LD4NetC0Loc=B8;modulemoduleSW0SW7,SW6,SW5,SW4,SW3,SW2SW1inputBTN0outputLD3,LD2,LD1,wirea0,a1,a2,a3,a4,a5,a6,a7;not(BTN0_L,BTN0);and(a0,BTN0_L,SW0);and(a1,BTN0,SW4);and(a2,BTN0_L,SW1);and(a3,BTN0,SW5);and(a4,BTN0_L,SW2);and(a5,BTN0,SW6);and(a6,BTN0_L,SW3);and(a7,BTN0,SW7);or(LD0,a0,a1)or(LD1,a2,a3)or(LD2,a4,a5)or(LD3,a6,a7)////AddstimulushereSW3=0;SW2=SW1=SW0=BTN0=#200SW7=SW6=SW5=SW4=BTN0=6AnvylUCFNETSW0LOC=V5;NETSW1LOC=U4;NETSW2LOC=V3;NETSW3LOC=P4;NETSW4LOC=R4;NETSW5LOC=P6;NETSW6LOC=P5;NETSW7LOC=NETLD0LOC=W3;NETLD1LOC=Y4;NETLD2LOC=Y1;NETLD3NetBTN0Loc=NETSW0NETSW0LOC=T10;#SW0NETSW1LOC=T9;#SW1NETSW2LOC=V9;#SW2NETSW3LOC=M8