組合邏輯電路的設(shè)計和分析1概述2編碼器3譯碼器4簡單數(shù)字顯示系統(tǒng)5其它定義：任一時刻的輸出僅僅取決于當(dāng)時的輸入，與電路原來的狀態(tài)無關(guān)，這樣的數(shù)字電路叫做組合邏輯電路。常用組合邏輯電路有以下幾種：

〔1〕編碼器〔2〕譯碼器〔3〕比較器〔4〕數(shù)據(jù)選擇器〔5〕三態(tài)輸出電路〔6〕加法器1概述2編碼器2.18-3編碼器2.2二－十進(jìn)制編碼器編碼器有普通編碼器和優(yōu)先編碼器，我們設(shè)計一個普通的8-3編碼器。

輸入信號輸出信號使能端口一、外觀及功能2.18-3編碼器

注：EN為1時編碼器工作二、其VHDL程序結(jié)構(gòu)體1實體architecturem2ofbmqisbeginprocess(a)beginifen='1'thencaseaiswhen"00000001"=>Y<="000";when"00000010"=>Y<="001";when"00000100"=>Y<="010";when"00001000"=>Y<="011";when"00010000"=>Y<="100";when"00100000"=>Y<="101";when"01000000"=>Y<="110";when"10000000"=>Y<="111";whenothers=>y<="000";endcase;elsey<="000";endif;endprocess;endm2;結(jié)構(gòu)體25.2.2二－十進(jìn)制編碼器

一、外觀及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entitybmqisport(A:instd_logic_vector(9downto0);

B:outstd_logic_vector(3downto0));endbmq;architecturem1ofbmqisbeginB<="0000"whenA="0000000001"else"0001"whenA="0000000010"else“0010"whenA="0000000100"else“0011"whenA="0000001000"else“0100"whenA="0000010000"else“0101"whenA="0000100000"else“0110"whenA="0001000000"else“0111"whenA=“0010000000"else“1000"whenA=“0100000000"else“1001"whenA=“1000000000"else“1111"endm1;結(jié)構(gòu)體實體3譯碼器3.13-8譯碼器3.2七段顯示碼譯碼器3.13-8譯碼器一、外觀及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entityymqisport(Y:instd_logic_vector(2downto0);EN:instd_logic;A:outstd_logic_vector(7downto0));endymq;architecturem1ofymqisbeginprocess(y)beginifen='1'thencaseyiswhen"000"=>A<="00000001";when"001"=>A<="00000010";when"010"=>A<="00000100";when"011"=>A<="00001000";when"100"=>A<="00010000";when"101"=>A<="00100000";when"110"=>A<="01000000";when"111"=>A<="10000000";whenothers=>A<="11111111";endcase;elseA<="11111111";Endif;endprocess;endm1;3.2七段顯示碼譯碼器一、外觀及功能二、其VHDL程序Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityxianisPort(C:instd_logic_vector(3downto0);D:outstd_logic_vector(6downto0));Endxian;

Architecturea1ofxianisBeginD<="0111111"whenC="0000"else--0"0000110"whenC="0001"else--1"1011011"whenC="0010"else--2"1001111"whenC="0011"else--3"1100110"whenC="0100"else--4"1101101"whenC="0101"else--5"1111101"whenC="0110"else--6"0000111"whenC="0111"else--7"1111111"whenC="1000"else--8"1101111"whenC="1001"else--9"0000000";Enda1;結(jié)構(gòu)體實體簡單數(shù)字顯示系統(tǒng)數(shù)字鍵盤顯示器顯示譯碼器二十進(jìn)制編碼器Libraryieee;Useieee.std_logic_1164.all;Useeee.std_logic_unsigned.all;EntityshuziisPort(X:instd_logic_vector(9downto0);Y:outstd_logic_vector(6downto0));Endshuzi;ArchitectureaofshuziisSignalZ:std_logic_vector(3downto0);ComponentxianPort(C:instd_logic_vector(3downto0);D:outstd_logic_vector(6downto0));endcomponent;ComponentbmqPort(A:instd_logic_vector(9downto0);B:outstd_logic_vector(3downto0));endcomponent;BeginU1:bmqPortmap(x,z);U2:xianPortmap(z,Y);Enda;U1:bmqPortmap(x,z);U2:xianPortmap(z,Y);例化過程：一、數(shù)據(jù)選擇器5.5其它libraryieee;useieee.std_logic_1164.all;entitymux41isport(A,B,C,D:instd_logic_vector(15downto0);Sel:intd_logic_vector(1downto0);Y:outstd_logic_vector(15downto0));endmux41;architectureFofmux41isbeginwithselselectY<=Awhen"00",Bwhen"01",Cwhen"10",Dwhenothers;endF; 二、八位二進(jìn)制比較器Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;ENTITYcmpabISPORT(A,B:instd_logic_vector(7downto0);Y1,Y2,Y3:outstd_logic);ENDcmpab;ARCHITECTUREaOFcmpabISBEGINY1<='1'whena=belse'0';--并行語句Y2<='1'whena>belse'0';Y3<='1'whena<belse'0';ENDa;時序邏輯電路的設(shè)計和分析2觸發(fā)器3計數(shù)器4分頻器5存放器1概述任一時刻的輸出不僅取決于當(dāng)時的輸入，而且還取決于電路原來的狀態(tài)，這樣的數(shù)字電路叫做時序邏輯電路。常用時序電路設(shè)計：

〔1〕JK型、T型和D型觸發(fā)器〔2〕移位存放器設(shè)計〔3〕計數(shù)器設(shè)計〔4〕分頻器設(shè)計1概述2觸發(fā)器2.1D觸發(fā)器2.2T觸發(fā)器2.3JK觸發(fā)器符號特性表2.1D觸發(fā)器LIBRARYIEEE;USEIEEE.std_logic_1164.all;EntityffDisport(clk,d:instd_logic;q:outstd_logic);EndffD;Architecturebody1offfdisbeginprocess(clk)beginifclk’eventandclk=’1’thenq<=d;endif;endprocess;endbody1;Architecturebody2offfdisbeginprocess(clk,d)beginifrising_edge(clk)thenq<=d;endif;endprocess;endbody2;符號特性表6.2.2T觸發(fā)器LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYfftISPORT(Cp,T:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDfft;ARCHITECTUREaOFfftISsignalqn:std_logic;BEGINprocess(cp)beginifcp'eventandcp='1'thenifT=’1’thenqn<=notqn;endif;endif;endprocess;q<=qn;ENDa;符號特性表2.3JK觸發(fā)器LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYffJKISPORT(Cp,J,K:INSTD_LOGIC;

q:OUTSTD_LOGIC);END

ffJK;ARCHITECTUREaOFffJKIS

signalqn:std_logic;

Signaltt:std_logic_vector(2downto1)BeginProcess(Cp)begintt<=J&K;ifCp’eventandCp=’1’thencasettiswhen“10〞=>qn<=‘1’;when“01〞=>qn<=‘0’;when“11〞=>qn<=notqn;whenothers=>null;Endcase;Endif;EndProcess;q<=qn;Enda;練習(xí)題：在JK觸發(fā)器的結(jié)構(gòu)體中是否可以用with–select語句。計數(shù)器的種類很多。按計數(shù)器中的觸發(fā)器是否同時翻轉(zhuǎn)分類，可以把計數(shù)器分為同步式和異步式兩種。如果按計數(shù)過程中計數(shù)器中的數(shù)字增減分類，有可以分為加法計數(shù)器和減法計數(shù)器?？稍隹蓽p的計數(shù)器為可逆計數(shù)器。有時也用計數(shù)器的計數(shù)容量來區(qū)分各種不同的計數(shù)器，如十進(jìn)制計數(shù)器、二十四進(jìn)制計數(shù)器和六十進(jìn)制計數(shù)器等。一、24進(jìn)制加法計數(shù)器

計數(shù)器LIBRARYIeee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount24ISPORT(en,clk:INSTD_LOGIC;qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--個位數(shù)計數(shù)qb:outSTD_LOGIC_VECTOR(1DOWNTO0));--十位數(shù)計數(shù)ENDcount24;實體結(jié)構(gòu)體ARCHITECTUREa1OFcount24ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(1DOWNTO0);beginifclk'eventandclk='1'thenifen='1'theniftma="1001"thentma:="0000";tmb:=tmb+1;Elsiftmb="10"andtma="0011"thentma:="0000";tmb:="00";elsetma:=tma+1;endif;endif;endif;qa<=tma;qb<=tmb;endprocess;ENDa1;二、60進(jìn)制加法計數(shù)器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount60ISPORT(en,clk:INSTD_LOGIC;qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--個位數(shù)計數(shù)qb:outSTD_LOGIC_VECTOR(2DOWNTO0);--十?dāng)?shù)計數(shù)rco:OUTSTD_LOGIC);--計數(shù)進(jìn)位ENDcount60;實體結(jié)構(gòu)體ARCHITECTUREaOFcount60ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(2DOWNTO0);beginifclk'eventandclk='1'thenifen='1'thenrco<=tmb(0)andtmb(2)andtma(0)andtma(3)anden;iftma="1001"thentma:="0000";iftmb=“101〞thentmb:=“000〞;elsetmb:=tmb+1;endif;elsetma:=tma+1;endif;endif;endif;qa<=tma;qb<=tmb;endprocess;ENDa;結(jié)論:該計數(shù)器為十進(jìn)制加計數(shù)器4分頻器〔加法4MHz-1hz分頻器〕狀態(tài)圖時序圖10000100110<1>一個3bits的計數(shù)器，它所能計數(shù)的范圍為0~7〔=23-1〕。同理，nbits的計數(shù)器所能計數(shù)范圍為0~2n-1。<2>Q0、Q1、Q2的波形頻率分別為時鐘脈沖信號Clk的1/2、1/4、1/8，由此可以知道，nbits的計數(shù)器可獲得的最低分頻頻率為時鐘脈沖信號Clk的1/2n。<3>對于4MHz頻率信號，假設(shè)作為加法計數(shù)器電路的時鐘脈沖信號Clk，那么電路