1、Floating-Point Unit,Copyright 2009 Texas Instruments. All rights reserved.,Appendix E TMS320C28x MCU Workshop,Learning Objectives,Architecture floating-point format, registers, and pipeline Instructions instruction types, delay slots, parallel instructions, RPTB, floating-point flags Instruction Sum

2、mary,IEEE Single-Precision Floating-Point Format,* Normal Positive and Negative Values are Calculated as: ( -1 ) s x 2 (E-127) x 1.M+/- 1.7 x 10 -38 to +/- 3.4 x 10 +38,The Normalized IEEE numbers have a hidden 1; thus the equivalent signed integer resolution is the number of mantissa bits + sign +

3、1,23-bit Mantissa (Implicit Leading Bit + Fraction Bits),8-bit Exponent (Biased),1 Sign Bit (0 = Positive, 1 = Negative),IEEE Single-Precision Floating-Point Format (IEEE 754),Most widely used standard for floating-point Standard number formats, Special values (NaN, Infinity) Rounding modes 2p instr

4、uction NOP ; 1 cycle delay ; ; Can use R2H ;,MPYF32 R2H, R1H, R0H ; 2p instruction NOP ; 1 cycle delay for MPYF32 ; ; Can use R2H ; ;,MPYF32 R2H, R1H, R0H ; 2p instruction ADDF32 R3H, R3H, R1H ; 1 cycle delay for MPYF32 ; - MPYF32 completes, R2H valid NOP ; 1 cycle delay for ADDF32 ; - ADDF32 comple

5、te, R3H valid ;,MPYF32 R2H, R1H, R0H ; 2p instruction ADDF32 R3H, R3H, R1H ; 1 cycle delay for MPYF32 ; - MPYF32 completes, R2H valid MOV32 *XAR7, R2H ; 1 cycle delay for ADDF32 ; - ADDF32 complete, R3H valid ;,MPYF32 R2H, R1H, R0H ; 2p instruction ADDF32 R3H, R3H, R1H ; 1 cycle delay for MPYF32 ; -

6、 MPYF32 completes, R2H valid MOV32 *XAR7, R2H ; 1 cycle delay for ADDF32 ; - ADDF32 complete, R3H valid ; - MOV32 complete,Math Operations: 2p (2 pipelined) cycles Can be launched every cycle Result is valid 2 instructions later,Move Operation: 1 cycle,Parallel Instructions,ADDF32 R3H, R3H, R1H | MO

7、V32 *XAR7, R3H,Single Instruction Single Opcode Performs 2 Operations Example: Add + Parallel Store,Parallel Bars Indicate A Parallel Instruction,Note: cycle information is given for both operation,Multiply and Store Parallel Instruction,MPYF32 R2H, R1H, R0H | MOV32 *XAR3, R2H,; 2p/1 instruction ; ;

8、 Can use R2H,; Before: R0H = 2.0, R1H = 3.0, R2H = 10.0 MPYF32 R2H, R1H, R0H ; 2p/1 instruction | MOV32 *XAR3, R2H ; ; Can use R2H ; After: R2H = ? *XAR3 = ?,; Before: R0H = 2.0, R1H = 3.0, R2H = 10.0 MPYF32 R2H, R1H, R0H ; 2p/1 instruction | MOV32 *XAR3, R2H ; ; Can use R2H ; After: R2H = R1H * R0H

9、 = 3.0 * 2.0 ; *XAR3 = 10.0,Math Operations: 2p (2 pipelined) cycles Can be launched every cycle Result is valid 2 instructions later Move Operation: 1 cycle,Parallel Instruction: MOV32 used the value of R2H before the MPY32 update,Multiply and Store Parallel Instruction,; MPYF32 R2H, R1H, R0H ; 2p/

10、1 instruction | MOV32 *XAR3, R2H ; - MOV32 complete MOV32 R1H, *XAR4 ; Delay for MPYF32 ; - R2H updated, R1H updated ADDF32 R2H, R2H, R1H ; Can use R2H ;,Math Operations: 2p (2 pipelined) cycles Can be launched every cycle Result is valid 2 instructions later Move Operation: 1 cycle,Parallel Instruc

11、tion: MOV32 used the value of R2H before the MPY32 update,Using Floating-Point Status Flags,LVF,LUF,NF,ZF,rsvd,TF,ZI,Floating-Point Status Register STF (32-bits),NI,RND F32,rsvd,SHDWS,Latched overflow Loop if (R1H R0H),Program control is through the C28x status register (ST0) flags Use MOVST0 to cop

12、y FPU flags to ST0,Repeat Block,Improves performance of block algorithms (FFT, IIR) 0 cycles after the first iteration,; find the largest element and ; put its address in XAR6 .align 2 NOP RPTB VECTOR_MAX_END, AR7 MOVL ACC,XAR0 MOV32 R1H,*XAR0+ MAXF32 R0H,R1H MOVST0 NF,ZF MOVL XAR6,ACC,LT VECTOR_MAX

13、_END:,RC(15),RE(7),RSIZE(7),30,Repeat Block Register RB (32),RA,RAS,29:23,22:16,15:0,31,RC: Repeat CountBlock Executes RC+1,RA = 1 RPTB Active,RE: End address,RSIZE: RPTB Block Size Max: 127 x 16 WordsMin: 8 words (odd aligned) 9 words (even aligned),RA = 0,Hardware Manages RB,Assembler Checks Size

14、Align stack PUSH RB ; Save RB if used PUSH AR1H:AR0H ; Save if used PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 PUSH XT SPM 0 ; Set C28 modes CLRC AMODE CLRC PAGE0,OVM SAVE RNDF32=1 ; FPU registers ; set FPU mode . .,Full Context Save,. . RESTORE ; FPU registers POP XT ; Restore regi

15、sters POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H POP RB ; Restore RB NASP ; Un-align stack IRET ; Return,Full Context Restore,22 Cycles (worst case if all registers are saved),19 Cycles (worst case if all registers are restored),Note: The following critical registers are aut

16、omatically saved on an interrupt: ACC, P, XT, ST0, ST1, IER, DP, AR0, AR1, PC,. . MOV32 R7H,*-SP ; Restore R0H to R7H . . MOV32 R0H,*-SP MOV32 STF,*-SP ; Restore STF POP XT ; Restore XT POP XAR7 ; Restore XAR0 to XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H:AR0H MOVW DP,#PIE SETC INTM

17、; Disable Interrupts POP RB ; Restore RB NASP ; Un-align Stack Pointer MOV AL,*-SP MOV PIEIERn,AL ; Restore PIE Interrupt Priority IRET ; Return From Interrupt,Full Context Restore,_LowerPriorityISR: MOVW DP,#PIE ; Set PIE Interrupt Priority MOV AL,PIEIERn OR IER,#INTn_PRIORITY_MASK AND IER,#IER_PRI

18、ORITY_MASK MOV PIEIERn,#PIEIERn_PRIORITY_MASK MOV PIEACK,#0 xFFFF MOV *SP+,AL ASP ; Align Stack Pointer PUSH RB ; Save RB CLRC INTM ; Enable Interrupts PUSH AR1H:AR0H ; Save XAR0 to XAR7 PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 PUSH XT ; Save XT MOV32 *SP+,STF ; Save STF MOV32 *SP