1、第七章,同步電路設(shè)計及與異步信號交互問題,Outline,Synchronous Design vs. Asynchronous Design Asynchronous Interface Metastability Slow clock domain to fast clock domain Fast clock domain to slow clock domain General Clock Strategy,About Synchronous Design,What is synchronous design circuit? All clocked element, such as

2、flip flops (FFs) or registers, share a common clock signal (a globally distributed clock) Data changes based on clk edges Example: clk reaches to R1 and R2 at the same time,How to guarantee synchronous design for millions of gates in layout? Clock Tree Synthesis (CTS) supported by EDA company used t

3、o solve the problem,Clock Tree Synthesis,CTS tool will do: Parasitic extraction Delay calculation Timing analysis Placement Routing Topologies: H tree .,Pros and Cons,Pros Fully supported by EDA tools Static timing analysis tools are designed to report timing problem on one-clock synchronous designs

4、 Easy to implement Cons Noise caused by the gates on the clock path Clock skew Increased chip area Increased power,About Asynchronous Design,Transition can be done at any time - Not controlled by any global or local clock,Asynchronous Design cont.,Designing a purely asynchronous circuit is a nontriv

5、ial and potentially hazardous task How to avoid race and hazard conditions? Not supported by EDA tools Handshaking protocols result in complexity,Outline,Synchronous Design vs. Asynchronous Design Asynchronous Interface Metastability Slow clock domain to fast clock domain Fast clock domain to slow c

6、lock domain General Clock Strategy,Metastability,Observed: asynchronous inputs in synchronous systems lead to system failure (also called synchronization failure),Metastability - cont,An asynchronous input which can change at any time with respect to the clock edges of the synchronous system. When a

7、 FF input signal is changing state at or near the instant of active clk edge occurring.,Metastable state The output of the device does not reach either of the valid logic levels but between the two for a time that is long compared with the normal timing delays of the device or may even oscillate. If

8、 the signal bdat1 is propagated to the rest of the design before it comes to a stable state, synchronous failure will occur. More cases in real ASIC design world Input data from UART, SSI, devices to another device/chip Asynchronous external reset,Metastability - cont,Avoid Metastability Case I,Case

9、 1: signal from slow CLK domain enter into fast CLK domain Common approach is 2 stage FF synchronizer Extra clock cycle added to delay. This must be acceptable in application if this type of solution is chosen,Two Stage FF Synchronizer,Two FFs Synchronizer cont.,Two Stage FF Synchronizer cont.,But a

10、 synchronizer does not eliminate the possibility of metastable failure. It only limits its occurrence within the synchronizer and thereby minimize its effect on the system Bad news - building a perfect synchronizer that always delivers a legal answer is impossible!,MTBF,Mean time between failures (M

11、TBF) for a single flip-flop :,MTBF =,(nsec),T : the period of the synchronizing clock Ts : is the setting time : the mean rate of arrival of data edges and To : describe the metastability performance of the flip-flop,A Shift Register Synchronizer: A chain of (N+1) flip-flops,Assumed that a metastabl

12、e state is transferred along the chain of flip-flops by simple sampling,Simplified Equation,tp is the propagation delay of a flip-flop The more stage, the more stable. But introduce longer delay,MTBF =,Avoid Metastability Case II,Case II: Signal from Fast Clock Domain into Slow Clock Domain Problem:

13、 a signal from a fast clock domain only asserted for one fast clock cycle before it can be sampled into a slow clock domain.,Can not solve the problem!,If using 2 stage FF synchronizer:,Common Practical Solution Handshaking Protocol,Example 1: To assert control signal for a period of time that excee

14、ds the cycle time of the sampling clk (hand shaking),Data-Path Synchronization,Passing multi-bit data from one clk domain to another A Common mistake: Try to apply a simple synchronized flip-flop approach to synchronizing bused signals. Problem: No guarantee that the bus data alignment is preserved.

15、 (This could be due to the different loading on each bit of data.) Consequently, bus data are incorrectly sampled Common practical solutions: To have a data_valid signals accompany the bus (handshaking) Use asynchronous FIFO (First In First Out memories),Data-Path Synchronization cont.,Method 1: to

16、have a data_valid signal accompany the bus Data_valid signal is not asserted until a comfortable timing margin after all the bus bits have transitioned. To synchronize data_valid signal only and use it to indicate Bus bits are stable Condition: the rate of sampling clk must be much higher than the r

17、ate of updates on the Bus,Data-Path Synchronization cont.,Method 2: use FIFOs Dual port memory: dual port SRAM or FF array The data first written to it shall also be the first one read from it Store (write) data using one clk domain and retrieve (read) data using another clk domain,What is FIFO,Init

18、ial state,4 data have been written in fifo, but none has been read,4 data are written in fifo, while one data has been read,FIFO Structure,Asynchronous Signals in FIFO Design,FIFO can not be read when there is no data in it - empty FIFO can not be written when the number of data in it reaches FIFO d

19、epth full FIFO full or empty signals are generated by 2 address pointers, wptr and rptr, which are generated from 2 different clk domains, wclk and rclk respectively. wptr and rptr are asynchronous signals,FIFO Design: Asynchronous Case cont.,Suggestion: FIFO pointers implemented as Gray-code counte

20、r which only change one bit at a time Example of binary and Gray codes: Binary code: 00, 01, 10, 11 Gray code: 00, 01, 11, 10 Will either be the old value or the new value if asynchronous signal comes in the middle of a Gray code counter transition The Gray-code pointers are synchronized by the cloc

21、k from the opposite clock domain to generate FIFO full /empty flags wptr = rptr FIFO empty wptr + 1 = rptr FIFO full,Outline,Synchronous Design vs. Asynchronous Design Asynchronous Interface Metastability Slow clock domain to fast clock domain Fast clock domain to slow clock domain General Clock Str

22、ategy,General Clock Strategy for SoC Design,Prefer synchronous design The tools for logic synthesis and Clock Tree Synthesis do their best work on synchronous design Static timing analysis tools are designed to report timing problem on one-clock synchronous designs The task of DFT scan insertion is

23、simplified,General Clock Strategy - cont,Use the smallest number of clk domains Problem with more clk domains Complicate synthesis scripts False path, multi cycle path Complicate DFT scan insertion Separated scan chains Increase the possibility of encountering metastability,Clock Strategy for SoC De

24、sign - cont,Try to group asynchronous design, if there is, any into separate modules Easily identify them in backend design and given special treatment Easy for design review,General Clock Strategy cont.,Avoid latches Latch : level-sensitive Transparent during its on time Advantage: fast ( clock rate can be higher than the worst case critical path) Allowing one stage to pass slack or to borrow time from other stage Complicated to perform STA due to the ability of being transparent when enabled A latch input is an end