1、硬件描述語言VHDL及其應(yīng)用,哈工大微電子中心 王 進(jìn) 祥,電話：6415979-806,2020/9/16,2,一、目的,了解目前電子設(shè)計(jì)系統(tǒng)方法及流程 了解/掌握綜合與驗(yàn)證工具 能用VHDL設(shè)計(jì)復(fù)雜功能電路,二、內(nèi)容,高層次設(shè)計(jì)概述 如何寫優(yōu)化的VHDL代碼 examples SoC設(shè)計(jì)方法學(xué) 設(shè)計(jì)工具使用,三、如何學(xué)習(xí)本課程,帶著實(shí)際課題學(xué)習(xí)，多提問題，一起分析、討論,2020/9/16,3,一、高層次設(shè)計(jì)概述,EDA工具發(fā)展 設(shè)計(jì)方法 深亞微米設(shè)計(jì)問題 測(cè)試綜合（可測(cè)性設(shè)計(jì)） Top-down設(shè)計(jì)流程 硬件描述語言 綜合 VHDL設(shè)計(jì)小結(jié),2020/9/16,4,1.1 EDA工具發(fā)展

2、,2020/9/16,5,1.1 EDA工具發(fā)展（Cont.）,CAD: 邏輯圖輸入、邏輯模擬、電路模擬、版圖設(shè)計(jì)和版圖驗(yàn)證分別進(jìn)行，需要對(duì)兩者結(jié)果進(jìn)行多次比較、修改。設(shè)計(jì)規(guī)模較小,CAE: 集邏輯圖輸入、邏輯模擬、測(cè)試碼生成、電路模擬、版圖設(shè)計(jì)、版圖驗(yàn)證等工具一體，構(gòu)成一個(gè)較完整的IC設(shè)計(jì)系統(tǒng),EDA: HDL取代邏輯輸入，邏輯網(wǎng)表由綜合工具自動(dòng)產(chǎn)生，可管理性增強(qiáng)，易于維護(hù)和數(shù)據(jù)交換,SoC: 采用深亞微米工藝生產(chǎn)技術(shù)，基于平臺(tái)設(shè)計(jì)和IP復(fù)用技術(shù)，時(shí)序收斂性為首要目標(biāo),2020/9/16,6,自頂向下設(shè)計(jì)方法（Top-down） :系統(tǒng)行為設(shè)計(jì) 結(jié)構(gòu)設(shè)計(jì) 邏輯設(shè)計(jì) 電路設(shè)計(jì) 版圖設(shè)計(jì),1.2

3、 設(shè)計(jì)方法,自底向上設(shè)計(jì)方法（Bottom-up）: 系統(tǒng)功能劃分 單元設(shè)計(jì) 功能模塊設(shè)計(jì) 子系統(tǒng)設(shè)計(jì) 系統(tǒng)總成,基于平臺(tái)設(shè)計(jì)方法（Platform-based）: SoC設(shè)計(jì)普遍采用的方法，SoC平臺(tái)和IPIntellectual Property,其它設(shè)計(jì): 嵌入式設(shè)計(jì)方法，層次式設(shè)計(jì)方法等,2020/9/16,7,1.3 深亞微米設(shè)計(jì)問題,連線延時(shí) 時(shí)序模型 器件模型 信號(hào)完整性 電磁干擾 功耗 設(shè)計(jì)工具,綜合優(yōu)化工具,布圖規(guī)劃工具,SDF,PDEF,SDF標(biāo)準(zhǔn)數(shù)據(jù)格式,PDEF物理設(shè)計(jì)交換格式,2020/9/16,8,1.4 測(cè)試綜合,目的： 集成電路的測(cè)試簡(jiǎn)單化 嵌入可測(cè)試結(jié)構(gòu)，加速

4、可測(cè)性設(shè)計(jì) 產(chǎn)品制造前就可評(píng)價(jià)設(shè)計(jì)的可測(cè)性 消除冗余邏輯 診斷不可測(cè)的邏輯結(jié)構(gòu),內(nèi)容： 測(cè)試嵌入、設(shè)計(jì)規(guī)則檢查、測(cè)試碼生成、故障模擬/診斷和輸出測(cè)試圖樣,測(cè)試綜合包括了使測(cè)試成功的每一步驟：如加入帶測(cè)試因素的電路，對(duì)邏輯綜合增加約束條件以滿足測(cè)試要求及對(duì)高級(jí)語言描述的可測(cè)結(jié)構(gòu)的綜合等都可歸結(jié)為測(cè)試綜合,2020/9/16,9,1.4 測(cè)試綜合（Cont.）,方法： Full Scan Partial Scan BIST Boundary Scan,標(biāo)準(zhǔn)/規(guī)范： IEEE 1149 IEEE P1500 VSIA Related Spec.,SoC可測(cè)試設(shè)計(jì)： IP可測(cè)試設(shè)計(jì) Glue Logi

5、c可測(cè)試設(shè)計(jì) 測(cè)試存取結(jié)構(gòu),分類： 1Pass 2Pass,2020/9/16,10,1.5 Top-down設(shè)計(jì)流程,PLANNING,SYNTHESIS,FLOORPLAN, P xout : out bit8); end component; signal ctlN1m1, ctlN1, ctl254, ctl255 : std_logic; signal ctlobf, synfb : std_logic; signal fbo, dout, synout, lstsfe, bout : bit8; signal cntout : rsInt; signal iffto, syndou

6、t : bit8; signal bmfo : rsbit8_vector(0 to N2 - 1);,5,2020/9/16,20,1.8 VHDL設(shè)計(jì)小結(jié)（Cont.）,begin u1 : control port map(reset, clk, ctlN1m1, ctlN1, ctl254, ctl255, ctlobf, synfb, cntout); u2 : syndrome port map(reset, clk, decin, synfb, syndout); u3 : bmexpand port map(reset, clk, syndout, cntout, synout

7、, lstsfe, bout); u4 : bmfftbuf port map(reset, clk, ctl255, synout, lstsfe, bmfo); u5 : ifft port map(reset, clk, ctlN1m1, ctlN1, ctl254, bmfo, iffto); u6 : fftobuf port map(reset, clk, ctlobf, iffto, fbo); u7 : decbuf port map(reset, clk, decin, dout); u8 : xor8 port map(fbo, dout, decout); end str

8、uctural;,6,2020/9/16,21,二、如何寫優(yōu)化的VHDL代碼,數(shù)據(jù)類型 并發(fā)/順序賦值語句 小結(jié) Process語句 資源共享 其它,2020/9/16,22,2.1 數(shù)據(jù)類型,2020/9/16,23,2.1 數(shù)據(jù)類型(Cont.),2020/9/16,24,2.1.1 賦值語句,i/signal t, s : bit; s = 1; - s = t;,ii/ signal c : bit_vector(0 to 3); signal d : bit_vector(3 downto 0); c = “1011”;,d = c; - ok ? c(0 to 3) = d(0 t

9、o 3) ok?,d = c; - ok ! c(0 to 3) = d(0 to 3) No!,2020/9/16,25,iii/ signal s, t, w, m : bit; signal c : bit_vector(0 to 3); c = “1011”; c = s ,c 1, 1 - s, 2- 1, 3 - 1); -Ok,2.1.1 賦值語句（Cont.）,2020/9/16,26,iv/ signal a_vec : bit_vector(0 to 11); a_vec = B”1100_0011_0011_1100”; a_vec = “1100001100111100

10、”; a_vec = X”C33C”; a_vec = X”C3_3C”;,2.1.1 賦值語句（Cont.）,2020/9/16,27,二進(jìn)制B（Binary） 八進(jìn)制O（Octal） 十六進(jìn)制X（Hexadecimal）,位串中的進(jìn)制表示：,2.1.1 賦值語句（Cont.）,2020/9/16,28,v/ signal A, B, C : bit_vector(3 downto 0); C = A and B;,2.1.1 賦值語句（Cont.）,2020/9/16,29,vi/ slice of array entity VHDL is port(A : in bit_vector(0

11、 to 7); outp : out bit); end VHDL; architecture E1 of VHDL is begin outp = A(5); end;,signal C : bit_vector(0 to 7); C(4) = 1; C(0 to 3) = “1001”;,2.1.1 賦值語句（Cont.）,2020/9/16,30,vii/ Composite data type type date is record year : integer range 1980 to 2030; month : integer range 1 to 12; day : integ

12、er range 1 to 30; end record; subtype bit8 is bit_vector(7 downto 0);,2.1.1 賦值語句（Cont.）,2020/9/16,31,vii/ Composite data type signal weekday, today : date; weekday.year = 2003; weekday.monty = 2; weekday.day = 14; today = weekday;,2.1.1 賦值語句（Cont.）,2020/9/16,32,2.1.2 數(shù)據(jù)類型轉(zhuǎn)換,強(qiáng)類型語言：VHDL具有豐富的數(shù)據(jù)類型，不同類型的

13、對(duì)象（信號(hào)、變量）不能直接賦值,經(jīng)常轉(zhuǎn)換的數(shù)據(jù)類型：std_logic, bit, std_ulogic, boolean, signed unsigned, std_logic_vector, bit_vector,數(shù)據(jù)類型轉(zhuǎn)換三種方法：類型標(biāo)記轉(zhuǎn)換法、 函數(shù)轉(zhuǎn)換法和常數(shù)轉(zhuǎn)換法,2020/9/16,33,類型標(biāo)記轉(zhuǎn)換法,std_logic and std_ulogic, std_logic_vector and signed std_logic_vector and unsigned integer and real等,signal a std_logic_vector(0 to 7); s

14、ignal b unsigned(0 to 7); b = unsigned(a);,2.1.2 數(shù)據(jù)類型轉(zhuǎn)換(Cont.),2020/9/16,34,函數(shù)轉(zhuǎn)換法,std_logic and bit std_ulogic and bit, boolean and bit, std_logic_vector and bit_vector integer and std_logic_vector/unsigned等,signal a std_logic_vector(0 to 7); signal b integer range 0 to 255; a = to_stdlogicvector(X”

15、AF”); b = conv_ingeter(a);,2.1.2 數(shù)據(jù)類型轉(zhuǎn)換(Cont.),2020/9/16,35,type typeconv_type is array(std_ulogiclow to std_ulogichigh) of bit; constant typeconv : typeconv_type := (0 | L = 0, 1 | H = 1, others = 0); signal s : std_ulogic; signal a : bit; a = typeconv(s);,常數(shù)轉(zhuǎn)換法,2.1.2 數(shù)據(jù)類型轉(zhuǎn)換(Cont.),2020/9/16,36,How

16、 to transform bit type to boolean type?,signal bitty : bit; signal booly : boolean; booly = (bitty = 1);,Discussion,2.1.2 數(shù)據(jù)類型轉(zhuǎn)換(Cont.),2020/9/16,37,2.1.3 邏輯運(yùn)算與關(guān)系運(yùn)算,運(yùn)算符: and, or, not, xor, nand, nor =, /=, , =,Discussion: What is the result of the following relational statement?,2020/9/16,38,2.1.4 算

17、術(shù)操作,運(yùn)算符: +， ， *， mod， /， rem,操作數(shù)類型: std_logic_vector, integer, signed, unsigned,use ieee.std_logic_unsigned.all;,2020/9/16,39,2.1.4 算術(shù)操作（Cont.）,signal a, b : std_logic_vector(3 downto 0); q1 = unsigned(a) + unsigned(b); q2 = unsigned(a) + signed(b); q3 = signed(a) + signed(b); q4 = a + b; q5 = (0 ,2

18、020/9/16,40,2.1.5 連字符和聚集,連字符：concatenation operator 聚集：aggregates,signal A, B : std_logic_vector(3 downto 0); signal C : std_logic_vector(7 downto 0); signal D : std_logic; C = A ,2020/9/16,41,C(7) 1, 6 = D, 5 downto 2 = 1, others = 0); C = “00000000”; -初始化,C 0);,2.1.5 連字符和聚集(Cont.),2020/9/16,42,2.2

19、 并發(fā)/順序賦值語句,并發(fā)賦值語句在architecture的begin和end之間，與書寫順序無關(guān)，每一條并發(fā)語句均可用一個(gè)process語句等價(jià),順序賦值語句只能在process和子程序的begin和end之間，它除信號(hào)賦值語句外，還有變量賦值,2020/9/16,43,2.2.1 并發(fā)賦值語句,D = A + E; A = B + C;,2020/9/16,44,2.2.1 并發(fā)賦值語句(Cont.),A = B + A;,并發(fā)賦值語句：,C = A; C = B;,組合邏輯環(huán)路！,Multi-driver, need resolved function,2020/9/16,45,2.2

20、.2 順序賦值語句,D = A + E; A = B + C;,2020/9/16,46,2.2.2 順序賦值語句(Cont.),C = A; C = B;,A = B + A;,組合進(jìn)程：No! 時(shí)序進(jìn)程：Ok!,2020/9/16,47,2.3 小結(jié),一個(gè)設(shè)計(jì)由entity和architecture描述 數(shù)據(jù)對(duì)象類型有bit, boolean, integer, std_logic等標(biāo)準(zhǔn)類型和用戶自定義類型 并發(fā)語句執(zhí)行與書寫順序無關(guān)（order independent） VHDL是一種強(qiáng)類型語言（類型不能自動(dòng)相互轉(zhuǎn)換） 元件例化語句不能在process中，if語句和for語句用于并發(fā)語句

21、時(shí)，只能是generate語句，并發(fā)語句無變量賦值語句,2020/9/16,48,2.3 小結(jié)(Cont.),entity shift is port( reset, clk : in std_logic; din : in std_logic; dout : out std_logic); end shift; architecture str of shift is component dff port(reset, clk : in std_logic; d : in std_logic; q : out std_logic); end component;,signal tv : st

22、d_logic_vector(0 to 7); begin for I in 0 to 7 generate if I = 0 generate u1 : dff port map(reset, clk, din, tv(0); end generate; if I 0 and I = 7 generate u2 : dff port map(reset, clk, tv(I 1), tv(I); end generate; end generate; dout = tv(7); end str;,2020/9/16,49,2.4 process,描述電路功能或行為。由于綜合后的電路對(duì)所有輸入

23、信號(hào)變化敏感，因此所有被讀信號(hào)均應(yīng)包含在敏感表中，否則，綜合前的模擬結(jié)果與綜合后的模擬結(jié)果不一致！,2020/9/16,50,2.4.1 syntax,process_label : process(sensitivity list) declarations; begin statements; - if, loop, case, subprogram call etc end process process_label;,2020/9/16,51,2.4.1 syntax,P1 : process(A, B) Begin D = A or B and C; End process P1;,

24、P1 : process(A, B, C) Begin D = A or B and C; End process P1;,2020/9/16,52,2.4.2 communication among process,architecture example,2020/9/16,53,2.4.3 if then else語句綜合,i/. 引入寄存器,entity dff is port (d : in std_logic; clk : in std_logic; q : out std_logic); End dff;,architecture rtl of dff is begin infe

25、r_reg : process(d, clk) begin if (clkevent and clk = 1) then q = d; end process infer; end rtl;,2020/9/16,54,2.4.3 if then else語句綜合(Cont.),ii/. 引入鎖存器,Infer_latch : process(A, B) begin if (A = 1) then x = B; end process infer_infer_latch;,Infer_latch : process(A, B) Begin x = 0; if (A = 1) then x = B

26、; end process infer_infer_latch;,隱含了A = 0時(shí) x = x; 不完全的else,2020/9/16,55,2.4.3 if then else語句綜合(Cont.),iii/. 組合電路,entity comb is port(a, b : in bit; select : in bit; y : out bit); end comb;,architecture arch of comb is begin process(a, b, select) begin if (select = 1) then y = b; else y = a; end if;

27、end process; end arch;,2020/9/16,56,2.4.3 if then else語句綜合(Cont.),iv/. 異步復(fù)位,process(reset, clk, d) Begin if (reset = 0) then q = 0; elsif (clkevent and clk = 1) then q = d; end if; end process;,2020/9/16,57,2.4.3 if then else語句綜合(Cont.),v/. 三態(tài)邏輯,signal s, sel, data : std_logic; process(sel, data) Be

28、gin if (sel = 1) then s = data; else s = Z; end if; end process;,1,2020/9/16,58,2.4.3 if then else語句綜合(Cont.),v/. 三態(tài)邏輯,architecture beh of tribuf is signal asel, bsel, a, b, s : std_logic; begin pa : process(asel, a) begin s = Z; if (asel = 1) then s = a; end if; end process pa;,2,pb : process(bsel,

29、 b) begin s = Z; if (bsel = 1) then s = b; end if; end process pb; end beh;,Multi driver!,2020/9/16,59,2.4.3 if then else語句綜合(Cont.),Discussion,signal a, b, use_b : bit; process(a, b, use_b) Begin if (use_b = 1) then s = b; elseif(use_b = 0) then s = a; end if; end process;,1,Latch?,2020/9/16,60,2.4

30、.3 if then else語句綜合(Cont.),Discussion,signal a, b, use_b : std_logic; process(a, b, use_b) Begin if (use_b = 1) then s = b; elseif(use_b = 0) then s = a; end if; end process;,2,Latch?,2020/9/16,61,2.4.3 if then else語句綜合(Cont.),Discussion,else assert false report “invalid use_b” severity error; end i

31、f; end process;,3,what?,signal a, b, use_b : std_logic; process(a, b, use_b) Begin if (use_b = 1) then s = b; elseif(use_b = 0) then s = a;,2020/9/16,62,2.4.3 if then else語句綜合(Cont.),vi/. 在一個(gè)進(jìn)程中，一個(gè)信號(hào)只能對(duì)應(yīng)一個(gè)三態(tài)驅(qū)動(dòng),process(b, ub, a, ua) Begin dout = Z; if (ub = 1) then dout = b; end if; if (ua = 1) then

32、dout = a; end if; end process;,2020/9/16,63,2.4.3 if then else語句綜合(Cont.),vii/. Z值使用規(guī)則,如：dout = Z and din;,如：if (sel = Z) then 相當(dāng)于 if false then,2020/9/16,64,2.4.3 if then else語句綜合(Cont.),vii/. if then else語句小結(jié),2020/9/16,65,2.4.4 case 語句,i/. syntax,case (expression) is when value = statements; when

33、value | value = statements; when value1 to value2 = statements; when others = statements; end case;,2020/9/16,66,2.4.4 case 語句(Cont.),ii/. case 語句規(guī)則,任意value互不相同,如無others分枝，必須窮盡所有可能的表達(dá)式值,如有others分枝，必須至少有一個(gè)表達(dá)值未列出,任意分枝中的語句可以有多條,2020/9/16,67,2.4.4 case 語句(Cont.),entity decoder is port(din : in std_logic

34、_vector(0 to 2); q : out std_logic_vector(0 to 7); end decoder; architecture ex of decoder is begin process(din) begin case (din) when “000” = q q q = “00000100”;,when “011” = q q q q q q = “-”; end case; end process; end ex;,2020/9/16,68,2.4.5 for loop語句,i/. 語法,loop_label : for loop_var in range lo

35、op sequential statements; end loop loop_label;,說明：loop_label可選，loop_var不需聲明，綜合時(shí)，循環(huán)語句將unrolled,Why loop statement ?,2020/9/16,69,2.4.5 for loop語句(Cont.),entity parsum is port(word : in std_logic_vector(0 to 7); par : out std_logic); end parsum; architecture addxor of parsum is begin process(word) var

36、iable ts : std_logic; begin ts : = 0;,for I in wordrange loop ts := ts xor word(I); end loop; par = ts; end process; end addxor;,Discussion: 如果ts為信號(hào)，結(jié)果是什么？,2020/9/16,70,2.4.6 數(shù)據(jù)對(duì)象,constant variable signal,i/. constant and variable,constant mask : std_logic_vector(0 to 7) := “00000000”; constant led_

37、zero : bit_vector(0 to 7) := X”7E”; variable tsum : std_logic_vector(3 downto 0);,2020/9/16,71,2.4.6 數(shù)據(jù)對(duì)象(Cont.),ii/. signal and variable,相同點(diǎn)：值可變，可綜合為邏輯或線,不同點(diǎn)：變量賦值有立即性，且只用于process和subprogram中（VHDL-1076-87），而信號(hào)除此之外，還可用于并行語句中,應(yīng)用：簡(jiǎn)單計(jì)算 signal 復(fù)雜計(jì)算 variable 中間結(jié)果 variable,2020/9/16,72,2.4.6 數(shù)據(jù)對(duì)象(Cont.),si

38、gnal a, b, c, x, y : short process(a, b, c) begin c = a; x = c + 2; c = b; y = c + 4; end process;,signal a, b, x, y : short process(a, b, c) variable c : short; begin c := a; x = c + 2; c := b; y = c + 4; end process;,2020/9/16,73,2.4.6 數(shù)據(jù)對(duì)象(Cont.),signal,variable,2020/9/16,74,2.4.6 數(shù)據(jù)對(duì)象(Cont.),ent

39、ity sigvar is port(a, b, c, d : std_logic; q : out std_logic; end sigvar; architecture sig of sigvar is signal int : std_logic; Begin process(a, b, c, d, int) begin int = a and b and c; q = int or d; end process; end sig;,entity sigvar is port(a, b, c, d : std_logic; q : out std_logic; end sigvar; a

40、rchitecture sig of sigvar is Begin process(a, b, c, d) variablel int : std_logic; begin int := a and b and c; q = int or d; end process; end sig;,2020/9/16,75,2.4.7 wait 語句,wait until, wait, wait on, wait for,wait語句表明了信號(hào)激活process的條件,在process中，如有wait語句，敏感表必須取消,在process中，如既無wait語句，也無敏感表，則不能正確模擬,綜合工具僅支

41、持wait until語句（引入寄存器）!,2020/9/16,76,2.4.7 wait 語句(Cont.),library ieee; Use ieee.std_logic_1164.all; entity count4 is port(updown : in std_logic; clk : in std_logic; dout : out integer range 0 to 15); end count4;,architecture behave of count4 is signal cnt : integer range 0 to 15; begin process begin

42、wait until clkevent and clk = 1;,if (updown = 1) then if (cnt = 15) then cnt = 0; else cnt = cnt + 1; end if; else if (cnt = 0) then cnt = 15; else cnt = cnt 1; end if; end if; end process; end behave;,2020/9/16,77,2.5 資源共享,硬件資源： 關(guān)系運(yùn)算：=，/=，= 算術(shù)運(yùn)算：+，*，/,每個(gè)運(yùn)算符均要消耗大量的硬件資源，并產(chǎn)生延時(shí)!,如何用最小的資源實(shí)現(xiàn)相同的功能 ？,2020/

43、9/16,78,2.5 資源共享(Cont.),i/. if (sel_a = 1) then z = a + t; end if; if (sel_a = 0) then z = b + t; end if; ,1,2020/9/16,79,2.5 資源共享(Cont.),i/. z = a + t when sel_a = 1 else b + t; 或 if (sel_a = 1) then z = a + t; else z = b + t; end if;,2,2020/9/16,80,2.5 資源共享(Cont.),ii/. dout := 0; found := false; f

44、or k in 1 to 4 loop if(found = false) then if (a(k) = 1) then dout := b(k) + c(k); found := true; end if; end if; end loop;,1,2020/9/16,81,2.5 資源共享(Cont.),ii/. t1 := 0; t2 := 0; found := false; for k in 1 to 4 loop if(found = false) then if (a(k) = 1) then t1 := b(k); t2 := c(k); found := true; end

45、if; end if; end loop; dout := t1 + t2;,2,2020/9/16,82,2.5 資源共享(Cont.),iii/. 多進(jìn)程 P1 ： process begin wait until clkevent and clk = 1; if (sel = “00”) then reg_0 = dA + dB; end if; end process P1;,1,P2 ： process begin wait until clkevent and clk = 1; if (sel = “01”) then reg_1 = dA - dB; end if; end pr

46、ocess P2;,2020/9/16,83,2.5 資源共享(Cont.),iii/. 多進(jìn)程 P3 ： process begin wait until clkevent and clk = 1; if (sel = “10”) then reg_2 = dB - dA; end if; end process P1;,2,dout = reg_0 when sel = “00” else reg_1 when sel = “01” else reg_2 when sel = “10” else 0;,資源：3個(gè)加法器/減法器，資源共享不能在多進(jìn)程間實(shí)現(xiàn)！,2020/9/16,84,2.5

47、 資源共享(Cont.),iv/. if(addr(31 downto 20) = “000000000001”) then,資源：兩個(gè)12位比較器,資源：兩個(gè)3位比較器+一個(gè)9位比較器,2020/9/16,85,2.5 資源共享(Cont.),v/. s(0) A 1) then s(k) = 1; else s(k) = 0; end if; end loop;,資源：1個(gè)減法器，7個(gè)比較器,說明：模擬時(shí)間長(zhǎng)，因?yàn)槊窟M(jìn)入循環(huán)均要計(jì)算一次減法；綜合時(shí)間也會(huì)較長(zhǎng)，因?yàn)榫C合工具要移去循環(huán)中的定值表達(dá)式,1,2020/9/16,86,2.5 資源共享(Cont.),v/. s(0) tv) the

48、n s(k) = 1; else s(k) = 0; end if; end loop;,資源：1個(gè)減法器，7個(gè)比較器,說明：模擬、綜合時(shí)間短,2,2020/9/16,87,2.5 資源共享(Cont.),v/. s(0) A) then s(k) = 1; else s(k) = 0; end if; end loop;,資源：0個(gè)減法器，7個(gè)比較器,說明：下標(biāo)運(yùn)算不產(chǎn)生額外資源消耗，綜合工具自動(dòng)用2 to 8與A比較；模擬、綜合時(shí)間短,3,2020/9/16,88,2.5 資源共享(Cont.),vi/. sum := 0; for k in 0 to 7 loop sum := sum

49、+ A(k); end loop; dout = sum;,1,8個(gè)加法器，8級(jí)加法器延遲,2020/9/16,89,2.5 資源共享(Cont.),vi/. cnt := 8; for l in 0 to 2 loop cnt := cnt/2; for k in 0 to cnt 1 loop A(k) := A(k*2) + A(k*2 + 1); end loop; end loop; dout = A(0);,2,7個(gè)加法器，3級(jí)加法器延遲,2020/9/16,90,2.6 其它,i/. 正確使用后到達(dá)的信號(hào) process(A_late, B, C, D) begin if (A_

50、late + B 24) then dout = C; else dout = D; end if; end process;,1,2020/9/16,91,2.6 其它(Cont.),i/. 正確使用后到達(dá)的信號(hào) process(A_late, B, C, D) begin if (A_late 24 - B) then dout = C; else dout = D; end if; end process;,2,2020/9/16,92,2.6 其它(Cont.),ii/. 仿真與綜合結(jié)果不匹配 process variable cnt : integer range 0 to 255;

51、 begin wait until clkevent and clk = 1; cnt := cnt + 1; dout = cnt; end process;,1,變量將引入額外的寄存器！,2020/9/16,93,2.6 其它(Cont.),ii/. 仿真與綜合結(jié)果不匹配 signal cnt : integer range 0 to 255; process begin wait until clkevent and clk = 1; cnt = cnt + 1; end process; dout = cnt;,2,但是，仿真時(shí)，當(dāng)cnt的值為255時(shí)，再一次進(jìn)入該process時(shí)，將

52、報(bào)告越界錯(cuò)誤！,2020/9/16,94,2.6 其它(Cont.),ii/. 仿真與綜合結(jié)果不匹配 signal cnt : integer range 0 to 255; process begin wait until clkevent and clk = 1; if (cnt = 255) then cnt = 0; else cnt = cnt + 1; end process; dout = cnt;,3,2020/9/16,95,2.6 其它(Cont.),iii/. 避免不必要的重復(fù)調(diào)用函數(shù) function add8(in1, in2 : bit_vector(7 downt

53、o 0) is return bit_vector(7 downto 0); ,sign_bit := add8(A, B)(7); lower_nibble := add8(A, B)(3 downto 0); ,2020/9/16,96,2.6 其它(Cont.),iv/. 元件例化端口映射問題 inst1 : comp1 port map(din_1 = 0; din_2 = con_A; dout = con_out);,當(dāng)某一輸入端口接固定電平時(shí)，必須引入中間信號(hào)，且中間信號(hào)不能在說明時(shí)賦初值！,1,2020/9/16,97,2.6 其它(Cont.),iv/. 元件例化端口映射問題

54、 component dff port(reset, clk : in std_logic; d : in std_logic; q, qn : out std_logic); end dff;,當(dāng)某一輸出端懸空時(shí)，應(yīng)連接open關(guān)鍵字！,u1 : dff port map(reset = reset, clk = clk; q = dout, qn = open);,2,2020/9/16,98,2.6 其它(Cont.),v/. 避免陣列方向錯(cuò)誤 signal data8 : bit_vector(0 to 7); signal dout : bit_vector(7 downto 0);

55、 dout = data8(7 downto 0);,2020/9/16,99,2.6 其它(Cont.),vi/. 避免低效率語句 signal : l1, l2 : bit; P1 : process(l1, l2, A, B, C, D) begin case (l1 ,Ok?,No!,1,2020/9/16,100,2.6 其它(Cont.),vi/. 避免低效率語句,signal : l1, l2 : bit; P3 : process(l1, l2, A, B, C, D) subtype twobits is bit_vector(0 to 1); begin case (two

56、bits(l1 ,2,2020/9/16,101,2.6 其它(Cont.),vii/. 桶移位寄存器,entity barrel_shifter is port(clk : in bit; din : in bit_vector(0 to 31); k : in integer range 0 to 31; dout : out bit_vector(0 to 31); end barrel_shifter;,architecture behave of barrel_shifter is begin process begin wait until clkevent and clk = 1

57、; dout = din(k to 31) ,上述模型不可綜合，k是031中任意的數(shù)，屬于不可計(jì)算的，但上述模型可仿真！,1,2020/9/16,102,2.6 其它(Cont.),vii/. 桶移位寄存器,architecture syn1 of barrel_shifter is begin process begin wait until clkevent and clk = 1; if (k = 0) then dout = din; else for l in 1 to 31 loop if (l = k) then dout = din(l to 31) ,2,2020/9/16,103,2.6 其它(Cont.),vii/. 桶移位寄存器,architecture syn2 of barrel_shifter is begin process begin wai