外文文獻1原文DDSDEVICESTOPRODUCEHIGHQUALITYWAVEFORMASIMPLE,EFFICIENTANDFLEXIBLESUMMARYDIRECTDIGITALFREQUENCYSYNTHESISDDSTECHNOLOGYFORTHEGENERATIONANDREGULATIONOFHIGHQUALITYWAVEFORMS,WIDELYUSEDINMEDICAL,INDUSTRIAL,INSTRUMENTATION,COMMUNICATIONS,DEFENSEANDMANYOTHERAREASTHISARTICLEWILLBRIEFLYDESCRIBETHETECHNOLOGY,ONITSSTRENGTHSANDWEAKNESSES,EXAMINESOMEAPPLICATIONEXAMPLES,ANDALSOINTRODUCEDSOMENEWPRODUCTSTHATCONTRIBUTETOTHEPROMOTIONINTRODUCTIONAKEYREQUIREMENTINMANYINDUSTRIESISANEXACTPRODUCTION,EASYOPERATIONANDQUICKCHANGEOFDIFFERENTFREQUENCIES,DIFFERENTTYPESOFWAVEFORMSWHETHERITISBROADBANDTRANSCEIVERREQUIRESLOWPHASENOISEANDEXCELLENTSPURIOUSFREEDYNAMICPERFORMANCEOFAGILEFREQUENCYSOURCE,ORFORINDUSTRIALMEASUREMENTANDCONTROLSYSTEMNEEDSASTABLEFREQUENCYEXCITATION,FAST,EASYANDECONOMICALTOPRODUCEADJUSTABLEWAVEFORMWHILEMAINTAININGPHASECONTINUITYCAPABILITIESARECRITICALTOADESIGNSTANDARD,WHICHISWHATTHEADVANTAGESOFDIRECTDIGITALFREQUENCYSYNTHESISFREQUENCYSYNTHESISTASKTHEGROWINGCONGESTIONOFTHESPECTRUM,COUPLEDWITHLOWERPOWERCONSUMPTION,QUALITYOFNEVERENDINGDEMANDFORHIGHERMEASURINGEQUIPMENT,THESEFACTORSREQUIRETHEUSEOFTHENEWFREQUENCYRANGE,REQUIRESABETTERUSEOFEXISTINGFREQUENCYRANGEARESULT,THESEARCHFORBETTERCONTROL,INMOSTCASES,BYMEANSOFFREQUENCYSYNTHESIZERFORFREQUENCYGENERATIONTHESEDEVICESUSEAGIVENFREQUENCY,FCOFTOGENERATEATARGETFREQUENCYANDPHASEFOUTTHEGENERALRELATIONSHIPCANBESIMPLYEXPRESSEDASFOUTXFCAMONGTHEM,THESCALEFACTORX,SOMETIMESKNOWNASTHENORMALIZEDFREQUENCYTHEEQUATIONISUSUALLYGRADUALAPPROXIMATIONOFTHEREALNUMBERALGORITHMSWHENTHESCALEFACTORISARATIONALNUMBER,TWORELATIVELYPRIMENUMBERSOUTPUTFREQUENCYANDREFERENCEFREQUENCYTHANTHEHARMONICHOWEVER,INMOSTCASES,XMAYBELONGTOABROADERSETOFREALNUMBERS,THEAPPROXIMATIONPROCESSISWITHINTHEACCEPTABLERANGEWILLBETRUNCATEDDIRECTDIGITALFREQUENCYSYNTHESIZERTHEFREQUENCYSYNTHESIZERAPRACTICALWAYTOACHIEVEISTHEDIRECTDIGITALFREQUENCYSYNTHESISOFDDFS,USUALLYREFERREDTOASDIRECTDIGITALSYNTHESISDDSTHISTECHNIQUEUSINGDIGITALDATAPROCESSINGTOGENERATEAFREQUENCYANDPHASEADJUSTABLEOUTPUT,THEOUTPUTANDAFIXEDFREQUENCYREFERENCECLOCKSOURCEFCRELATEDDDSARCHITECTURE,THEREFERENCEORTHESYSTEMCLOCKFREQUENCYDIVIDEDBYASCALEFACTORTOPRODUCETHEDESIREDFREQUENCY,THESCALEFACTORISCONTROLLEDBYTHEBINARYTUNINGWORDPROGRAMMABLEINSHORT,DIRECTDIGITALFREQUENCYSYNTHESIZERTOCONVERTABUNCHOFCLOCKPULSESINTOANANALOGWAVEFORM,USUALLYASINEWAVE,TRIANGLEWAVEORSQUAREWAVESHOWNINFIGURE1,ITSMAINPARTSTHEPHASEACCUMULATORTOPRODUCETHEOUTPUTWAVEFORMPHASEANGLEDATA,RELATIVETODIGITALCONVERTER,ABOVETHEPHASEDATAISCONVERTEDTOTHEINSTANTANEOUSOUTPUTAMPLITUDEDATA,ANDDIGITALTOANALOGCONVERTERDACTHEMAGNITUDEOFDATAINTOASAMPLEDANALOGDATAPOINTSFIGURE1DDSFUNCTIONOFTHESYSTEMBLOCKDIAGRAMFORTHESINEWAVEOUTPUT,RELATIVETODIGITALCONVERTERISUSUALLYASINELOOKUPTABLEFIGURE2PHASEACCUMULATORUNITCOUNTNARELATIVETOTHEFREQUENCYOFFC,ACCORDINGTOTHEFOLLOWINGEQUATIONTHENUMBEROFPULSESOFTHEFCMISTHERESOLUTIONOFTHETUNINGWORD2448NCORRESPONDSTOTHESMALLESTINCREMENTOFPHASECHANGEOFTHEPHASEACCUMULATOROUTPUTWORDFIGURE2TYPICALDDSARCHITECTUREANDSIGNALPATHWITHDACSCHANGINGNWILLIMMEDIATELYCHANGETHEOUTPUTPHASEANDFREQUENCY,SOTHESYSTEMHASITSOWNCONTINUOUSPHASECHARACTERISTICS,WHICHISONEOFTHEKEYATTRIBUTESOFMANYAPPLICATIONSNOLOOPSETTLINGTIME,WHICHISDIFFERENTFROMTHEANALOGSYSTEM,SUCHASPHASELOCKEDLOOPSPLLSDACISUSUALLYAHIGHPERFORMANCECIRCUIT,DESIGNEDSPECIFICALLYFORTHEDDSCOREPHASEACCUMULATORANDPHASEAMPLITUDECONVERTERINMOSTCASES,THERESULTSOFTHEDEVICEUSUALLYSINGLECHIPISGENERALLYREFERREDTOASTHEPUREDDSORTHECDDSACTUALDDSDEVICESAREGENERALLYMULTIPLEREGISTERS,INORDERTOACHIEVEADIFFERENTFREQUENCYANDPHASEMODULATIONSCHEMESUCHASPHASEREGISTER,THEIRSTORAGEPHASEOFINCREASEINTHEOUTPUTPHASEOFTHEPHASEACCUMULATORINTHISWAY,THECORRESPONDINGDELAYOUTPUTSINEWAVEPHASEINAPHASETUNINGWORDTHISISUSEFULFORPHASEMODULATIONAPPLICATIONSFORCOMMUNICATIONSYSTEMSTHERESOLUTIONOFTHEADDERCIRCUITDETERMINESTHENUMBEROFBITSOFTHEPHASETUNINGWORD,THEREFORE,ALSODECIDEDTODELAYTHERESOLUTIONINTEGRATEDINASINGLEDEVICEONTHEENGINEOFADDSANDADACHASBOTHADVANTAGESANDDISADVANTAGES,HOWEVER,WHETHERINTEGRATEDORNOT,NEEDADACTOPRODUCEULTRAHIGHPURITYHIGHQUALITYANALOGSIGNALDACWILLCONVERTDIGITALSINUSOIDALOUTPUTTOANANALOGSINEWAVEMAYBESINGLEENDEDORDIFFERENTIALSOMEOFTHEKEYREQUIREMENTSFORLOWPHASENOISE,EXCELLENTWIDEBANDWBANDNARROWBANDNB,SPURIOUSFREEDYNAMICRANGESFDR,ANDLOWPOWERCONSUMPTIONIFTHEEXTERNALDEVICE,THEDACMUSTBEFASTENOUGHTOHANDLETHESIGNAL,SOTHEBUILTINPARALLELPORTDEVICEISVERYCOMMONDDSANDOTHERSOLUTIONSTHEFREQUENCYANALOGPHASELOCKEDLOOPSPLLS,CLOCKGENERATOR,ANDTHEUSEOFFPGADYNAMICPROGRAMMINGOFTHEOUTPUTOFTHEDACBYEXAMININGTHESPECTRUMOFPERFORMANCEANDPOWEROFTHESETECHNOLOGIES,ASIMPLECOMPARISON,TABLE1SHOWSTHEQUALITATIVERESULTSOFTHECOMPARISONTABLE1DDSWITHCOMPETINGTECHNOLOGIESADVANCEDCOMPAREPOWERCONSUMPTIONSPECTRALPURITYREMARKSDDSLOWMIDDLEEASEOFTUNINGDISCRETEDACFPGAMIDDLEMIDDLEHIGHWITHTUNINGCAPABILITIESANALOGPLLMILDDLEHIGHDIFFICULTTUNINGPHASELOCKEDLOOPISAFEEDBACKLOOPANDITSCOMPONENTSAPHASECOMPARATOR,ADIVIDERANDAPRESSURECONTROLLEDOSCILLATORVCO,PHASECOMPARATORREFERENCEFREQUENCYANDOUTPUTFREQUENCYUSUALLYTHEOUTPUTFREQUENCYISNFREQUENCYWERECOMPAREDTHEERRORVOLTAGEGENERATEDBYTHEPHASECOMPARATORISUSEDTOADJUSTTHEVCO,THUSTHEOUTPUTFREQUENCYWHENTHELOOPISESTABLISHED,THEOUTPUTFREQUENCYAND/ORPHASEWITHTHEREFERENCEFREQUENCYTOMAINTAINAPRECISERELATIONSHIPPLLHASLONGBEENCONSIDEREDINAPARTICULARFREQUENCYRANGE,HIGHFIDELITYANDCONSISTENTSIGNALLOWPHASENOISEANDHIGHSPURIOUSFREEDYNAMICRANGESFDRAREIDEALFORAPPLICATIONSPLLCANNOTBEPRECISELYANDQUICKLYTUNINGTHEFREQUENCYOUTPUTWAVEFORM,ANDTHESLOWRESPONSE,WHICHLIMITSTHEIRAPPLICABILITYFORFASTFREQUENCYHOPPINGANDPARTOFTHEFREQUENCYSHIFTKEYINGANDPHASESHIFTKEYINGAPPLICATIONSOTHERPROGRAMS,INCLUDINGINTEGRATEDDDSENGINEFIELDPROGRAMMABLEGATEARRAYSFPGASASYNTHETICSINEWAVEOUTPUTWITHTHEOFFTHESHELFDACTHOUGHTHEPLLFREQUENCYHOPPINGPROBLEMCANBESOLVED,BUTTHEREOWNSHORTCOMINGSTHEDEFECTSOFTHEMAJORSYSTEMSWORKANDINTERFACEPOWERREQUIREMENTS,HIGHCOST,LARGESIZE,ANDSYSTEMDEVELOPERSMUSTALSOCONSIDERTHEADDITIONALSOFTWARE,HARDWAREANDMEMORYFOREXAMPLE,USINGTHEDDSENGINEOPTIONINTHEMODERNFPGATOGENERATETHE10MHZOUTPUTSIGNALDYNAMICRANGEIS60DBUPTO72KBMEMORYSPACEINADDITION,DESIGNERSNEEDTOACCEPTANDBEFAMILIARWITHTHESUBTLEBALANCEDDSCOREARCHITECTUREFROMAPRACTICALPOINTOFVIEWSEETABLE2,THANKSTOTHERAPIDDEVELOPMENTOFCMOSTECHNOLOGYANDMODERNDIGITALDESIGNTECHNIQUES,ASWELLASTHEIMPROVEMENTOFTHEDACTOPOLOGY,DDSTECHNOLOGYHASBEENABLETOACHIEVEUNPRECEDENTEDLOWPOWERCONSUMPTIONINAWIDERANGEOFAPPLICATIONS,SPECTRUMPERFORMANCEANDCOSTLEVELSALTHOUGHTHEPUREDDSPRODUCTSINPERFORMANCEANDDESIGNFLEXIBILITYTOACHIEVETHELEVELOFHIGHENDDACTECHNOLOGYANDFPGA,BUTTHEADVANTAGESOFDDSINTERMSOFSIZE,POWERCONSUMPTION,COSTANDSIMPLICITY,MAKINGITTHEPRIMARYCHOICEFORMANYAPPLICATIONSTABLE2BENCHMARKANALYSISSUMMARYFREQUENCYGENERATIONTECHNIQUE50MHZPHASELOCKEDLOOPDACFPGADDSSPECTRALPERFORMANCEHIGHHIGHMIDDLESYSTEMPOWERREQUIREMENTSHIGHHIGHMIDDLEDIGITALFREQUENCYTUNINGNOYESYESTUNINGRESPONSETIMEHIGHLOWLOWSOLUTIONSIZEMIDDLEHIGHLOWWAVEFORMFLEXIBILITYLOWMIDDLEHIGHCOSTMIDDLEHIGHLOWDESIGNREUSEMIDDLELOWHIGHIMPLEMENTATIONCOMPLEXITYMIDDLEHIGHLOWALSOBENOTEDTHATTHEDDSDEVICEFORDIGITALMETHODSTOPRODUCETHEOUTPUTWAVEFORM,ITCANSIMPLIFYSOMEOFTHEARCHITECTUREOFTHESOLUTION,ORTHEWAVEFORMOFDIGITALPROGRAMMINGTOCREATETHECONDITIONSUSUALLYWITHASINEWAVETOEXPLAINTHEFUNCTIONSANDWORKINGPRINCIPLEOFTHEDDS,BUTUSINGMODERNDDSICSCANEASILYGENERATEATRIANGLEWAVEORSQUAREWAVECLOCKOUTPUT,THEREBYELIMINATINGTHEFORMERCASETHELOOKUPTABLE,ANDTHELATTERCASETHEDACTHENEEDTOINTEGRATEASIMPLEANDACCURATEENOUGHPERFORMANCEANDLIMITATIONSOFTHEDDSIMAGEANDENVELOPESINXXXROLLOFFTHEACTUALOUTPUTOFTHEDACISNOTACONTINUOUSSINEWAVE,BUTASERIESOFPULSESWITHASINUSOIDALTIMEENVELOPETHECORRESPONDINGSPECTRUMISASERIESOFIMAGEANDSIGNALALIASINGIMAGEALONGTHESINX/XENVELOPEDISTRIBUTIONSEEFIGURE3|MARGIN|GRAPHTHENEEDFORTHEFILTERTOSUPPRESSFREQUENCIESOUTSIDETHETARGETBAND,BUTCANNOTINHIBITTHEHIGHLEVELINTHEPASSBANDALIASINGFOREXAMPLE,CAUSEDDUETODACNONLINEARTHENYQUISTCRITERIONREQUIRESTHATEACHCYCLEREQUIRESATLEASTTWOSAMPLINGPOINTSINORDERTOREBUILDTHEDESIREDOUTPUTWAVEFORMTHEMIRRORINGRESPONSEARISINGFROMSAMPLINGTHEOUTPUTFREQUENCYK,CLOCKOUTINTHISEXAMPLE,WHICHCLOCK2525MHZANDFOUT5MHZ,THEFIRSTANDSECONDMIRRORFREQUENCYAPPEARINSEEFIGURE3FCLOCKFOUT,O20MHZAND30MHZTHETHIRDANDFOURTHMIRRORFREQUENCYAT45MHZAND55MHZNOTE,SINX/XVALUEOFZEROATMULTIPLESOFTHESAMPLINGFREQUENCYWHENFOUTGREATERTHANTHENYQUISTBANDWIDTH1/2FCLOCK,THEFIRSTMIRRORFREQUENCYWILLAPPEARINTHENYQUISTBANDWIDTH,THEOCCURRENCEOFALIASINGSUCHAS15MHZSIGNALALIASINGDOWNTO10MHZCANNOTUSETHETRADITIONALQUISTANTIALIASINGFILTERTOFILTEROUTALIASINGMIRRORFREQUENCYFROMTHEOUTPUTSIN,INFIGURE3DDS,X/XROLLOFFINATYPICALDDSAPPLICATION,THEUSEOFALOWPASSFILTERTOSUPPRESSTHEMIRRORFREQUENCYRESPONSEOFTHEOUTPUTSPECTRUMTOMAKETHELOWPASSFILTERCUTOFFFREQUENCYTOREMAINATREASONABLELEVELS,ANDKEEPITSIMPLEFILTERDESIGN,AFEASIBLEAPPROACHISTHEUSEOFANECONOMICLOWPASSOUTPUTFILTERBANDWIDTHLIMITEDTOABOUT40OFTHEFREQUENCYOFCLOCKANYGIVENMIRRORFREQUENCYRELATIVETOTHEAMPLITUDEOFTHEFUNDAMENTALFORMULAOFSINX/XCALCULATIONBECAUSETHEFUNCTIONOFTHEFREQUENCYROLLOFF,THEBASICOUTPUTOFTHEAMPLITUDEANDTHEOUTPUTFREQUENCYISINVERSELYPROPORTIONALTODECREASEINTHEDDSSYSTEM,REDUCETHEAMOUNTOFDCNYQUISTBANDWIDTHRANGEOF392DBSIGNIFICANTREDUCTIONINFREQUENCYINTHEFIRSTMIRRORTHEFUNDAMENTAL3DBRANGEINORDERTOSIMPLIFYTHEDDSAPPLICATIONFILTERING,FREQUENCYPLANMUSTBEFORMULATEDANDANALYZEDTOMIRRORTHEFREQUENCYANDMAGNITUDEOFTHESINX/XRESPONSEINTHEOUTANDCLOCKTARGETFREQUENCYSPECTRUMREQUIREMENTSOTHERUNWANTEDFREQUENCIESINTHEOUTPUTSPECTRUMSUCHASINTEGRALANDDIFFERENTIALLINEARITYERROROFTHEDAC,THESURGEOFENERGYASSOCIATEDWITHTHEDACANDCLOCKFEEDTHROUGHNOISEDOESNOTFOLLOWTHESINX/XROLLOFFRESPONSETHESEUNWANTEDFREQUENCIESWILLBEHARMONICANDSPURIOUSENERGYINTHEOUTPUTSPECTRUMINMANYPLACESBUTITSMAGNITUDEISGENERALLYFARBELOWTHEMIRRORFREQUENCYRESPONSEDDSDEVICESTOTHEGENERALBACKGROUNDNOISE,SUBSTRATENOISE,THERMALNOISEEFFECTS,GROUNDCOUPLINGANDOTHERSIGNALSOURCECOUPLINGFACTORCUMULATIVEPORTFOLIODECISIONSDDSDEVICES,THENOISEFLOORPERFORMANCEOFSTRAYANDJITTERBYTHECIRCUITBOARDLAYOUT,POWERQUALITY,ANDMOSTIMPORTANTLYENTERTHEPROFOUNDIMPACTOFTHEQUALITYOFTHEREFERENCECLOCKSHAKETHEEDGEOFTHEPERFECTCLOCKSOURCEWILLBETHEPRECISETIMEINTERVAL,THEINTERVALWILLNEVERCHANGEOFCOURSE,THISISNOTPOSSIBLEEVENTHEBESTOSCILLATORISALSOTHEIDEALCOMPONENTSCONSTITUTE,WITHNOISEANDOTHERDEFECTSQUALITYANDLOWPHASENOISECRYSTALOSCILLATORJITTERPICOSECOND,ANDISBUILTUPFROMONEMILLIONTHENUMBEROFCLOCKEDGETHEFACTORSLEADINGTOJITTEREXTERNALINTERFERENCE,THERMALNOISE,THEOSCILLATORCIRCUITINSTABILITYANDPOWER,GROUNDANDOUTPUTCONNECTIONSBRING,ALLTHESEFACTORSWILLINTERFEREWITHTHETIMINGCHARACTERISTICSOFTHEOSCILLATORINADDITION,THEOSCILLATORBYTHEEXTERNALMAGNETICFIELDORELECTRICFIELDANDTHENEARBYTRANSMITTERRFINTERFERENCEOSCILLATORCIRCUIT,ASIMPLEAMPLIFIER,INVERTERORBUFFERTOSIGNALADDITIONALJITTERTHEREFORE,THECHOICEOFALOWJITTER,ANDTHEEDGEOFSTEEPSTABLEREFERENCECLOCKOSCILLATORISCRITICALHIGHERFREQUENCYREFERENCECLOCKALLOWSALARGERSAMPLE,ANDDIVIDETOSOMEEXTENT,REDUCETHEJITTER,BECAUSETHESIGNALTODIVIDEALONGTIMETOPRODUCETHESAMEAMOUNTOFJITTER,WHICHCANREDUCETHEJITTERONTHESIGNALPERCENTAGENOISEINCLUDINGTHEPHASENOISETHESAMPLINGSYSTEMNOISEDEPENDSONMANYFACTORS,THEMOSTIMPORTANTFACTORISTHEREFERENCECLOCKJITTER,THISJITTERPERFORMANCEOFPHASENOISEONFUNDAMENTALSIGNALINTHEDDSSYSTEM,THEREGISTEROUTPUTOFTHETRUNCATEDPHASEMAYBRINGTHESYSTEMERRORCODETHEBINARYWORDDOESNOTLEADTOTHETRUNCATIONERRORBUTFORNONBINARYWORD,PHASENOISETRUNCATIONERRORINTHESPECTRUMSPURIOUSSPURIOUSFREQUENCY/AMPLITUDEDEPENDSONTHECODEWORDQUANTIFICATIONANDLINEARITYERROROFTHEDACWILLBEBROUGHTTOTHESYSTEMHARMONICNOISETIMEDOMAINERRORSUCHASOWEDTOTHERED/OVERSHOOTANDCODEERRORSWILLINCREASETHEOUTPUTSIGNALDISTORTIONAPPLICATIONDDSAPPLICATIONSCANBEDIVIDEDINTOTWOCATEGORIESREQUIREAGILEFREQUENCYSOURCEFORDATACODINGANDMODULATIONAPPLICATIONS,COMMUNICATIONSANDRADARSYSTEMSREQUIREMEASUREMENTOFTHEUNIVERSALFREQUENCYSYNTHESIZERFEATURESANDPROGRAMMABLETUNING,SCANNING,ANDMOTIVATIONALSKILLS,INDUSTRIALANDOPTICALAPPLICATIONSBOTHCASES,THETRENDTOWARDHIGHERSPECTRALPURITYLOWPHASENOISEANDHIGHERSPURIOUSFREEDYNAMICRANGE,ALSOLOWPOWERANDSMALLSIZEREQUIREMENTSTOACCOMMODATETHEREMOTEORDEMANDFORBATTERYPOWEREDDEVICESMODULATION/DATAENCODING,ANDSYNCHRONIZATIONOFTHEDDSDDSPRODUCTSFIRSTAPPEAREDONTHERADARANDMILITARYAPPLICATIONSANDTHEDEVELOPMENTOFSOMEOFITSCHARACTERISTICSPERFORMANCEIMPROVEMENTS,COSTANDSIZE,ETCDDSTECHNOLOGYISBECOMINGMOREPREVALENTINTHEMODULATIONANDDATAENCODINGAPPLICATIONSTHISSECTIONWILLDISCUSSTHETWODATAENCODINGSCHEMEINTHEDDSSYSTEMBINARYFREQUENCYSHIFTKEYINGBFSK,ORREFERREDTOASFSKONEOFTHEMOSTSIMPLEFORMOFDATAENCODINGTHELAUNCHOFTHEDATAISACONTINUOUSCARRIERFREQUENCYINTWODISCRETEFREQUENCYBINARYONE,IE,PASSNUMBER,ABINARY0,NAMELY,THETRANSFORMATIONBETWEENTHESPACEFIGURE4SHOWSTHERELATIONSHIPBETWEENTHEDATAANDTRANSMITSIGNALSFIGURE4BINARYFSKMODULATIONBINARY1AND0FORTWODIFFERENTFREQUENCIESF0ANDF1,RESPECTIVELYTHISENCODINGSCHEMECANBEEASILYDDSDEVICEONBEHALFOFTHEOUTPUTFREQUENCYOFTHEDDSFREQUENCYTUNINGWORDCHANGETOF0ANDF1,WILLLAUNCHTHE1AND0TOTRANSFORMTHEOUTPUTFREQUENCYSHALLDEDICATEDPINFSELECT,CONTAININGTHEAPPROPRIATETUNINGWORDREGISTERSSEEFIGURE5FIGURE5AD9834ORAD9838DDSTUNINGWORDSELECTORREALIZATIONOFTHEFSKENCODINGPHASESHIFTKEYINGPSKISASIMPLEFORMOFDATAENCODINGINPSK,THECARRIERFREQUENCYREMAINSTHESAME,BYCHANGINGTHEPHASEOFTHETRANSMITTEDSIGNALTOTRANSMITINFORMATIONCANTAKEADVANTAGEOFAVARIETYOFPROGRAMSTOACHIEVEPSK,THEEASIESTWAYISOFTENREFERREDTOASBINARYPSKBPSK,USINGONLYTWOSIGNALPHASE0LOGIC1AND180LOGIC0MEMBERSSTATEDEPENDSONTHESTATUSOFTHEFORMERONEIFTHEWAVEPHASEREMAINSUNCHANGED,THESIGNALSTATEWILLREMAINTHESAMELOWORHIGHWAVEPHASECHANGE180,IE,PHASEINVERSION,THESIGNALSTATEWILLCHANGELOWINTOHIGHORHIGHTOLOWPSKCODINGINDDSPRODUCTSCANBEEASILYACHIEVED,BECAUSEMOSTDEVICESHAVEASEPARATEINPUTREGISTERPHASEREGISTER,ANDPHASEVALUESCANBELOADEDTHISVALUEISADDEDDIRECTLYTOTHECARRIERPHASE,WITHOUTCHANGINGITSFREQUENCYCHANGETHECONTENTSOFTHEREGISTERWILLBEMODULATEDCARRIERPHASE,RESULTINGINAPSKOUTPUTFORAPPLICATIONSTHATREQUIREHIGHSPEEDMODULATION,BUILTINPHASEREGISTEROFTHEAD9834ANDAD9838ALLOWPSELECTPINSIGNALTRANSFORMATION,ACCORDINGTONEEDMODULATEDCARRIERINTHEPRELOADEDPHASEREGISTERSTHEMORECOMPLEXTHEPSKFOUROREIGHTWAVEPHASETHUS,WHENEVERTHEPHASECHANGEOFBINARYDATATRANSFERRATEWILLBEHIGHERTHANTHEBPSKMODULATIONINTHEFOURPHASEMODULATIONQUADRATUREPSK,INTHEPHASEANGLEOF0TO90,90AND180EACHPHASETOTRANSFORMTHETWOSIGNALSMAYREPRESENTAFACTORAD9830,AD9831,AD9832,ANDTHEAD9835PROVIDESFOURPHASEREGISTERS,CANBECONTINUOUSLYUPDATEDREGISTEROFDIFFERENTPHASESHIFT,THECOMPLEXPHASEMODULATIONSCHEMETHEUSEOFSYNCHRONOUSMODEOFMULTIPLEDDSDEVICESTOACHIEVETHEI/QMULTIPLEDDSCOMPONENTSTOACHIEVETHEMANYAPPLICATIONSOFTHEI/QSINEWAVEORSQUAREWAVESIGNALOFKNOWNPHASERELATIONSHIPBETWEENTWOORMORESYNCHRONOUSMODEACOMMONEXAMPLEISTHESAMEPHASEANDQUADRATUREMODULATIONI/QINTHISTECHNIQUE,THEPHASEANGLEOF0AND90FROMTHECARRIERFREQUENCYSIGNALINFORMATIONTORUNTWOSEPARATEDDSCOMPONENTS,YOUCANUSETHESAMESOURCECLOCKTOOUTPUTCANDIRECTLYCONTROLANDMANIPULATETHESIGNALOFTHEPHASERELATIONSHIPINFIGURE6,WITHAREFERENCECLOCKONTHEAD9838DEVICEPROGRAMMINGTHERESETPINISUSEDTOUPDATETHETWODEVICESINTHISWAY,YOUCANACHIEVEASIMPLEI/QMODULATIONRESETAFTERPOWERANDINITIALIZEDBEFOREANYDATATOTHEDDSTRANSMISSIONDDSOUTPUTRESULTSCANBEPLACEDINAKNOWNPHASE,MAKINGITACOMMONREFERENCEPOINTOFVIEW,INORDERTOSYNCHRONIZEMULTIPLEDDSDEVICESWHENNEWDATAISSENTTOMULTIPLEDDSDEVICES,THEDDSCANREMAINRELEVANTPHASERELATIONSHIP,ORBYTHEPHASEOFFSETREGISTERCANPREDICTTHERELATIVEPHASESHIFTBETWEENTHEADJUSTMENTSOFMULTIPLEDDSTHEAD983XSERIESOFDDSPRODUCTSHAVEA12PHASERESOLUTION,THEEFFECTIVERESOLUTIONOF01FIGURE6SYNCHRONIZETHETWODDSCOMPONENTSAUTHORBRENDANCRONINBRENDANCRONINANALOGCOMADICOREPRODUCTSANDTECHNOLOGIESCPT,APRODUCTMARKETINGENGINEERBRENDANJOINEDTHEADI,IN1998ANDWORKEDFORSIXYEARSINTHEINDUSTRIALANDAUTOMOTIVEPRODUCTSSECTOR,ASMIXEDSIGNALDESIGNENGINEERSBRENDANISCURRENTLYTHEMAINLINEARANDRELATEDTECHNOLOGIES外文文獻1翻譯DDS器件產生高質量波形簡單、高效而靈活摘要直接數字頻率合成DDS技術用于產生和調節(jié)高質量波形，廣泛用于醫(yī)學、工業(yè)、儀器儀表、通信、國防等眾多領域。本文將簡要介紹該技術，說明其優(yōu)勢和不足，考察一些應用示例，同時介紹一些有助于該技術推廣的新產品。簡介許多行業(yè)中一個關鍵的需求是精確產生、輕松操作并快速更改不同頻率、不同類型的波形。無論是寬帶收發(fā)器要求具有低相位噪聲和出色的無雜散動態(tài)性能的捷變頻率源，還是工業(yè)測量和控制系統(tǒng)需要穩(wěn)定的頻率激勵，快速、輕松、經濟地產生可調波形并同時維持相位連續(xù)性的能力都是至關重要的一項設計標準，而這正是直接數字頻率合成技術的優(yōu)勢所在。頻率合成的任務。不斷增多的頻譜擁堵，加上對功耗更低、質量更高的測量設備的永無止境的需求，這些因素都要求使用新的頻率范圍，要求更好地利用現有頻率范圍。結果，人們尋求對頻率產生進行更好的控制，多數情況下，均是借助于頻率合成器這些器件利用一個給定頻率,FC來產生一個相關的目標頻率（和相位）FOUT其一般關系可以簡單地表示為FOUTXFC其中，比例因子X,有時也被稱為歸一化頻率該等式通常利用實數逐步逼近的算法實現。當比例因子為有理數時，兩個相對質數（輸出頻率和基準頻率）之比將諧波相關。但在多數情況下，X可能屬于更廣泛的實數集，逼近過程一旦處于可接受的范圍之內即會被截斷。直接數字頻率合成頻率合成器的一種實用型實現方式是直接數字頻率合成DDFS,通常簡稱為直接數字合成DDS這種技術利用數字數據處理來產生一個頻率和相位可調的輸出，該輸出與一個固定的頻率參考或時鐘源FC相關。在DDS架構中，參考或系統(tǒng)時鐘頻率由一個比例因子分頻來產生所需頻率，該比例因子由二進制調諧字可編程控制。簡言之，直接數字頻率合成器將一串時鐘脈沖轉換成一個模擬波形，通常為一個正弦波、三角波或方波。如圖1所示，其主要部分為相位累加器（產生輸出波形相位角度的數據），相數轉換器,（將上述相位數據轉換為瞬時輸出幅度數據），以及數模轉換器DAC（將該幅度數據轉換成采樣模擬數據點）。圖1DDS系統(tǒng)的功能框圖對于正弦波輸出，相數轉換器通常為一個正弦查找表（圖2）。相位累加器以N為單位計數，并根據以下等式產生一個相對于FC的頻率其中M為調諧字的分辨率（24至48位）N為對應于相位累加器輸出字最小增量相位變化的FC的脈沖數圖2典型的DDS架構和信號路徑（帶DAC）由于更改N會立即改變輸出相位和頻率，因此，系統(tǒng)自身具有相位連續(xù),特點，這是許多應用的關鍵屬性之一。無需環(huán)路建立時間，這與模擬系統(tǒng)不同，如鎖相環(huán)PLL。DAC通常為一個高性能電路，專門針對DDS內核（相位累加器和相幅轉換器）而設計。多數情況下，這樣結果形成的器件（通常為單芯片）一般稱為純DDS或CDDS。實際的DDS器件一般集成多個寄存器，以實現不同的頻率和相位調制方案。如相位寄存器，其存儲的相位內容被加在相位累加器的輸出相位上。這樣，可以對應于一個相位調諧字延遲輸出正弦波的相位。對于通信系統(tǒng)相位調制應用，這非常有用。加法器電路的分辨率決定著相位調諧字的位數，因此，也決定著延遲的分辨率。在單個器件上集成一個DDS引擎和一個DAC既有優(yōu)點也有缺點，但是，無論集成與否，都需要一個DAC來產生純度超高的高品質模擬信號。DAC將數字正弦輸出轉換為一個模擬正弦波，可能是單端，也可能是差分。一些關鍵要求是低相位噪聲、優(yōu)秀的寬帶WB和窄帶NB無雜散動態(tài)范圍SFDR以及低功耗。如果是外部器件，則DAC必須足夠快以處理信號，因此，內置并行端口的器件非常常見。DDS與其他解決方案其他產生頻率的方法包括模擬鎖相環(huán)PLL,時鐘發(fā)生器和利用FPGA對DAC的輸出進行動態(tài)編程。通過考察頻譜性能和功耗，可以對這些技術進行簡單的比較，表1以定性方式展示了比較結果。表1DDS與競爭技術高級比較功耗頻譜純度備注DDS低中易于調諧分立式DACFPGA中中高具有調諧能力模擬PLL中高難以調諧鎖相環(huán)是一種反饋環(huán)路，其組成部分為一個相位比較器,一個除法器和一個壓控制振蕩器VCO相位比較器將基準頻率與輸出頻率（通常是輸出頻率的N分頻）進行比較。相位比較器產生的誤差電壓用于調節(jié)VCO，從而輸出頻率。當環(huán)路建立后，輸出將在頻率和/或相位上與參考頻率保持一種精確的關系。PLL長期以來一直被認為是在特定頻帶范圍內要求高保真度和穩(wěn)定信號的低相位噪聲和高無雜散動態(tài)范圍SFDR應用的理想選擇。由于PLL無法精確、快速地調諧頻率輸出和波形，而且響應較慢，這限制了它們對于快速跳頻和部分頻移鍵控和相移鍵控應用的適用性。其他方案，包括集成DDS引擎的現場可編程門陣列FPGAS配合現成DAC以合成輸出正弦波雖然可以解決PLL的跳頻問題，但也存在自身的缺陷。主要系統(tǒng)缺陷包括較高的工作和接口功耗要求、成本較高、尺寸較大，而且系統(tǒng)開發(fā)人員還須考慮額外的軟件、硬件和存儲器問題。例如，利用現代FPGA中的DDS引擎選項，要產生動態(tài)范圍為60DB的10MHZ輸出信號，需要多達72KB的存儲器空間。另外，設計師需要接受并熟悉細微權衡和DDS內核的架構。從實用角度來看（見表2），得益于CMOS工藝和現代數字設計技術的快速發(fā)展以及DAC拓撲結構的改進，DDS技術已經能在廣泛的應用中實現前所未有的低功耗、頻譜性能和成本水平。雖然純DDS產品不可能在性能和設計靈活性上達到高端DAC技術與FPGA相結合的水平，但DDS在尺寸、功耗、成本和簡單性方面的優(yōu)勢使其成為許多應用的首要選擇。表2基準分析小結頻率產生技術50MHZ鎖相環(huán)DACFPGADDS頻譜性能高高中系統(tǒng)功耗要求高高低數字頻率調諧無是是調諧響應時間高低低解決方案尺寸中高低波形靈活性低中高成本中高低設計重用中低高實現復雜度中高低同時需要指出，由于DDS器件從根本上