1、1Digital Logic Design and ApplicationLecture #13Three-State DevicesMultiplexerDemutiplexerUESTC, Spring 20136.6 Three-State Devices2three-state outputs: High, Low, Hi-ZVarious three-state buffers Non-inverting, active-high enablenon-inverting, active-low enableinverting, active-high enableinverting,

2、 active-low enable3Independent enable74X125: Active low, un-inverted bufferIndependent enable74X126:Active high, un-inverted bufferMSI three-state buffers 6.6 Three-State Devices4SDATASELP_LSELQ_LSELR_LSELS_LSELT_LSELU_LSELV_LSELW_LTypical three-state devices go into the Hi-Z state faster than they

3、come out of the Hi-Z state.Design control logic to ensure a dead time on the party line.Using the enable inputs of 74x138 1-bit party line (同線)5EN1EN2_L, EN3_Lmax(tpLZmax, tpHZmax)min(tpZLmin, tpZHmin)SSRC2:001237SDATAP0P1P2P3P7Dead TimeP420 Figure 6-5362. Standard MSI Three-State Buffers74x541commo

4、n enable inputs, active low兩個(gè)公共使能端，低電平使能，Schmitt trigger, non-inverting施密特觸發(fā)輸入，輸出不反相7Driver applicationDB0:7DataBus8A1B1DIRData can be transferred in either direction.P423 Figure 6-57 DIRG_LBus TransceiverThree-state transceiverData can be transferred in either direction.6.7 Multiplexer10Digital Swi

5、tch Multi-SwitchData Select 數(shù)據(jù)選擇器 ab. MUX 2-to-1MuxXYS控制輸入Z數(shù)據(jù)輸入Z=SX+SYS=0 Z=XX=1 Z=Y1. General description of MUX6.7 MultiplexerDesign a 4-to-1 MUX114-to-1MuxD0D3Z數(shù)據(jù)輸入S1 S0 控制輸入Truth tableS1 S0 Z0011D0D1D2D301016 inputs and 1 out putZ= D0+ D1+ D2+ D3S1S0 S1S0 S1S0 S1S0m0 m1 m2 m3Z=( miDi)1. General

6、description of MUX6.7 MultiplexerDesign a 8-to-1MUX128-to-1MuxD0D7ZS2 S1 S0 10 inputs and 1 out putZ=( miDi)S2 S1 S0 00001111D0D1D2D3D4D5D6D7Truth tableZ00110011010101011. General description of MUXS2S1S0 S2S1S0S2S1 S0 S2S1 S0S2 S1S0S2 S1S0S2 S1 S0S2 S1 S0D0D1D2D3D4D5D6D7136.7 MultiplexerENSELD0Dn-1

7、YEnableSelect n data sources1-bitdata output1-bit1-bitGeneral description of MUX6.7 MultiplexerGeneral description of MUX14ENSELD0Dn-1YEnableSelect n data sources1-bitm-bit data output m-bit Sometimes there are more than 1 bit in every sourcen input m-bit MUXN 輸入 m-bit 多路復(fù)用器n-1n-1n-1General descript

8、ion of MUX156.7 Multiplexer并行地將第j個(gè)數(shù)據(jù)源的b位全部選通 Enable on all the b-bits6.7 MultiplexerGeneral description of MUX16Sometimes there are more than 1 bit in every sourceExample：Design a 2 input 4-bit MUX3Y3A3B2A2B1A1B4Y4A4BENSELD0D1YEnableSelect 4-bitAB1-bit17InputsEN_L S1 X0 00 1 0 0 0 01A 2A 3A 4A1B 2B

9、3B 4BTruth table for a 74x157Outputs1Y 2Y 3Y 4Y74x157, 2-Input, 4-bit Multiplexer2. Standard MSI MultiplexersG_LS=0: Y=A;S=1: Y=B.Logic circuit Fig. 6-6118EN_L C B A Y Y_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D774x151 Truth tableA Lo

10、w BC High 8-inputs1-bitEN有效時(shí)： 2. Standard MSI Multiplexers19D0D1D2D3D6D7D4D5Y:原碼輸出卡諾圖2. Standard MSI MultiplexersEN有效時(shí)： 74x151, 8-input multiplexer8-to-1MUX212. Expanding Multiplexersexpand the number of bitsRealize 8-input, 16-bit MultiplexerExpanding form 1-bit to 16-bitNeed 16 74x151s each chip h

11、andle one bitSelect inputs would be connected to C,B,A of each chipNotice: fanout ability of select field driving 16 loadsENYYABCD0D774x151iDj第j個(gè)數(shù)據(jù)源的第i位數(shù)據(jù)Bit-i D source j3. Expanding Multiplexers22Realize 8-input, 16-bit MultiplexerEN_LENCBAD7D0Y0Y0_LENCBAD7D0Y15Y15_L151 0151 15DB15D7:15D0DB0D7:0D0S

12、EBC:ASEBC:ASEBC:A233 Expanding Multiplexersexpand the number of data sourcesRealize 32-input, 1-bit Multiplexerdata sources from 8 to 32, need 4 chipsHow to assign select inputs? divide into high-order bits and low-order bitsHigh-order bitsdecoder select chipLow-order bits C,B,A of each chipOutput u

13、sing OR gateThink of three-state outputsP437 Figure 6-62 ENYYABCD0D774x15124Build 32-input, 1-bit Multiplexer using 74x151ENC,B,AD7D0ENC,B,AD7D0ENC,B,AD7D0ENC,B,AD7D0DB7:0DB15:8DB23:16DB31:242-to-4decoderS2:0S4,3254. Realize Logic Circuit by using MultiplexerWhen device is enable,Sum of mintermsENAB

14、CD0D1D2D3D4D5D6D7YY74x151Example1. Use 74x151 torealize logic function: F = (A,B,C)(0,1,3,7)CBAVCCF26Example2. Use 74x151 to realize logic functionF = (W,X,Y,Z)(0,1,3,7,9,13,14) 降維：由4維3維YZWX00 01 11 10000111101111111YWX00 01 11 100110ZZZZZ0WXY(zd1+z d0)d0=1，d1=1，填1；若d0=1，d1=0，填z；若d0=0，d1=1，填z；若d0=0，

15、d1=0，填0；27YWX00 01 11 100110ZZZZZ00 2 6 4 1 3 7 5 ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZ說明：用具有n位地址輸入端的多路復(fù)用器，可以產(chǎn)生任何形式的輸入變量數(shù)不大于n+1的組合邏輯函數(shù)。Example2. Use 74x151 to realize logic functionF = (W,X,Y,Z)(0,1,3,7,9,13,14) 28Example2. Use 74x151 to realize logic functionF = (W,X,Y,Z)(0,1,3,7,9,13,14) F = WXYZ+

16、WXYZ+WXYZ+WXYZ+WXYZ+WXYZ+WXYZW X Y F 0 0 00 0 10 1 11 1 10 0 11 0 1X X X1ZZZZZ0Truth table74X15129ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZExample2. Use 74x151 to realize logic functionF = (W,X,Y,Z)(0,1,3,7,9,13,14) F的降維卡諾圖74X151的卡諾圖305. De-multiplexerRoute the bus data to one of m destinations多路 復(fù)用器 SR

17、CASRCBSRCZ多路 分配器 BUSDSTADSTBDSTZSRCSELDSTSELDST : destinationSRC : sourceSEL : select31ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_L數(shù)據(jù)輸入 SRC EN_LDSTSEL0DSTSEL1DSTSEL2地址選擇The enable input is connected to the data line.數(shù)據(jù)輸入 SRC EN_Lbinary decoder used as demultiplexerOne decoder chip handles one bitbinary decoder used as demultiplexer32SRCUse 74x138 as a 1-bit 1-to-8 DemuxG2B_LABC10 0110 00100Y1_L10 0110 00Yi_L(i1)1Quiz:數(shù)據(jù)接到高電平有效的是能斷，輸出的時(shí)序圖？33Use 74x139 as a 1-bit, 4-output demultiplexerbinary decoder used as de-multi