1、OctoberRevised January 7-StageRippleCarryBinaryGeneralThe CD4024BC is a 7-stage ripple-carry binary counter. Widesupplyvoltagerange: 3.0VtoBuffered outputs are externally available from stages 1Highnoiseimmunity: 0.45VDD(typ.) through 7. The counter is reset to its logical “0” stage by alogical “1”

2、on the reset input. The counter is advanced oneLowpowerTTLcompatibility: Fanoutof2driving74L count on the negative transition of each clock pulse.or 1 driving 74LSHighspeed: 12MHzinputpulserateVDD VSS Order 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lelastic Dual

3、-In-Line Package (PDIP), JEDEC MS-001, 0.300” DevicesalsoavailableinTandReel.Specifybyappendingthesuffixletter“X”totheordering PinAssignmentsforDIPandTop 1999 Fairchild Semiconductor LogicLogicInputFlip-floplogic(1of7identicalBlock (NoteConditions (NoteDC Supply Voltage (VDD)0.5 to 18 VDC DC Supply

4、Voltage (VDD)3to15VDC Input Voltage (VIN)0.5 to VDD 0.5 VDC Input Voltage (VIN)0toVDDVDC Storage Temperature Range (TS)65C to 150C Operating Temperature Range (TA)40Cto85C Power Dissipation (PD)Note 1: “Absolute um Ratings” are those values beyond which theDual-In-700mW safetyofthedevicecannotbeguar

5、anteed,theyarenotmeanttoimplythe devices should be operated at these limits. The table of Small 500mW mended Operating Conditions” and “Electrical Characteristics” Lead conditionsforactualdeviceNote2:V 0Vunless otherwise(Soldering, 10 seconds) DCElectricalCharacteristics(NoteQuiescentDeviceVDD 5V VD

6、D10V VDD LOWLevelOutput|lO|1 A VDD 5V VDD VDD 000 HIGHLevelOutput|lO|1 A VDD 5V VDD VDD 5 VLOWLevelInput|lO|1VDD 5V, VO 0.5V or 4.5V VDD 10V,VO 1.0V or 9.0V VDD15V,VO1.5Vor13.5V246 VHIGHLevelInput|lO|1VDD 5V,VO 0.5V or 4.5V VDD 10V, VO 1.0V orVDD15V,VO 1.5Vor369 V (Note3)VDD 5V, VO 0.4V VDD 10V,VO V

7、DD 15V,VO (Note3)VDD 5V, VO 4.6V VDD10V,VO9.5VVDD15V,VO InputVDD 15V,VIN VDD 15V,VIN Note3:IandIaretested oneoutputataACElectricalCharacteristics (NoteTA 25C,CL 50pF,RL 200k,tr and tf 20nsunlessotherwisetPHL, PropagationDelayVDD toQ1VDD VDD tTHL, VDD VDD VDD tWL,MinimumInputPulseVDD VDD VDD tRCL, In

8、putRiseandFallVDD VDD VDD 8umInputPulseVDD 5VDD 4VDD 5ResetPropagationDelayVDD VDD VDD Reset Minimum Pulse VDD VDD VDD InputCapacitance(NoteAny5Note4:ACParametersareguaranteedbyDCcorrelatedNote5:CapacitanceisguaranteedbyperiodicPhysicalPhysical Dimensions inches (millimeters) unless otherwise 14-Lea

9、dSmallOutlineIntegratedCircuit(SOIC),JEDECMS-120,0.150”NarrowBody Package Number M14APhysicalPhysical Dimensions inches (millimeters) unless otherwise noted 14-lasticDual-In-LinePackage(PDIP),JEDECMS-001,0.300”Wide Package Number N14ALIFE SUPPORT FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRI

10、TICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THEOFFAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1. Lifesupportdevices or systems aredevices or systems which, (a) are intended for surgical implant into the body,or(b)supportorsustainlife,and(c)whose

11、failure to perform when properly used in accordance with instructionsfor useprovidedinthelabeling,canberea- sonably expected to result in a significant injury to the 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonablyexpectedtocausethefailureofthelifesupport deviceorsystem,or toaffectitss