DigitalLogicCircuits數(shù)字邏輯電路知到章節(jié)測試答案智慧樹2023年最新南京理工大學(xué)第一章測試Thenumberofvaluesthatcanbeassignedtoabitare(

)

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twoComparedtoanalogsystems,digitalsystems(

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arelesspronetonoiseThetermbitmeans(

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bothanswers(b)and(c)Aquantityhascontinuousvalueis(

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ananalogquantityVerilogHDLisa(

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computerlanguageAcategoryofdigitalintegratedcircuitshavingfunctionsthatcanbealteredisknownasfixed-functionlogic.

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錯Dataareinformationonlyinnumeric.

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錯Twobroadtypesofdigitalintegratedcircuitsarefixed-functionandprogrammble.

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對Thenonrecurringengineering(NRE)costforanASICdesignisnormallylow.

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錯Thereisan“invalid”regionbetweentheinputrangesforlogic0andlogic1

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對第二章測試Forthebinarynumber10000,theweightofthecolumnwiththe1is(

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16The2’scomplementof1000is(

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1000Thefractionalbinarynumber0.11hasadecimalvalueof(

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?Thenumber1100inBCDis(

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invalidAnexampleofanunweightedcodeis(

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GraycodeAnexampleofanalphanumericcodeis(

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ASCIITheoverflowoccurswhenaddingthefollowing8-bittwo’scomplementnumber:01011101+00110001

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對TheoverflowdoesNOToccurwhenaddingthefollowing8-bittwo’scomplementnumber:10111111+11011111

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對Ingeneral,weneedatmostbitstoexpresstheproductwhenmultiplyingann-bitnumberbyanm-bitnumber.

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錯Anadditionoverflowsiftheaddends’signsarethesamebutthesum’ssignisdifferentfromtheaddends’.

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對第三章測試TheBooleanexpressionA

.

1isequalto(

).

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ATheBooleanexpressionA

+1isequalto(

).

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1TheBooleanequationAB+AC=A(B+C)illustrates(

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thedistributionlawTheassociativelawforadditionisnormallywrittenas(

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(A+B)+C

=A

+(B+C)ABooleanexpressionthatisinstandardSOPformis(

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haseveryvariableinthedomainineverytermAdjacentcellsonaKarnaughmapdifferfromeachotherby

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onevariableSOPstandardformisusefulforconstructingtruthtablesorforimplementinglogicinPLDs.

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對LogicsimplificationisstillusefulinnowadaysFPGAdesigns.

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錯Insynthesis,anetlistwillbegeneratedtodescribethecircuitcompletely.

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對InFPGAdesign,thestepthat“maps”thedesignfromthenetlisttofitittoatargetdeviceisknownas“programming”.

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錯第四章測試The74138decodercanalsobeusedas(

).

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aDEMUXAssumeyouwanttodecodethebinarynumber0011withanactive-LOWdecoder.Themissinggateshouldbe(

).

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aNANDgateToexpanda2-bitparalleladdertoa4-bitparalleladder,youmust(

).

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usetwo2-bitadderswiththecarryoutputofoneconnectedtothecarryinputoftheotherIfanhex-to-binarypriorityencoderhasits0,3,6,and14inputsattheactivelevel,theactive-HIGHbinaryoutputis(

).

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1110ThecontinuousassignmentassignOUT=

select?A:B;specifiestheconditionthatOUT=

()

ifselect=

1,elseOUT=

()

ifselect=

0.

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A,BConsidertheinitial

blockinthefollowing:initialbeginA=0;B=0;#10A=1;#20A=0;B=1;EndThenatt=30,Ais

changedto(

)andBto(

).

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0,1Theinitialstatementexecutesonlyonce,startingfrom

simulationtime0,andmaycontinuewithanyoperationsthataredelayedbyagiven

numberoftimeunits.

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對InVerilogHDL,thedefinitionsofmodulesareallowedtobenested.

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錯ThevaluezrepresentsanunknownlogicvalueinVerilogHDL.

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錯InVerilogHDL,~(1010)is(0101),and!(1010)is0.

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對第五章測試

TheoutputofaDlatchwillnotchangeif(

).

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EnableisnotactiveTheDflip-flopshownwill(

).

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toggleonthenextclockpulseFortheJ-Kflip-flopshown,thenumberofinputsthatareasynchronousis(

).

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2AssumetheoutputisinitiallyHIGHonaleadingedgetriggeredJ-Kflipflop.Fortheinputsshown,theoutputwillgofromHIGHtoLOWonwhichclockpulse?

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3Thetimeintervalillustratediscalled(

).

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tPLHTheadvantageofdynamicRAMoverstaticRAMisthat(

).

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itissimplerandcheaperAnasynchronous

resetsignalwilloverridetheclockonaFF.

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對InVerilogHDL,aninitialbehavioralstatementexecutesonlyonce.

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對InaMoore

model,theoutputsofthesequentialcircuitarenotsynchronizedwiththe

clock.

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錯TheoutputoftheMealy

machineisthevaluethatispresentimmediatelybeforethe

activeedgeoftheclock.

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對第六章測試TocauseaDflip-floptotoggle,connectthe(

).

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****A4-bitbinarycounterhasaterminalcountof(

).

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15Assumetheclockfora4-bitbinarycounteris80kHz.Theoutputfrequencyofthefourthstage(Q3)is(

).

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5kHzA4-bitparallel-in/parallel-outshiftregisterwillstoredatafor(

).

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1clockperiodAnadvantageofaringcounteroveraJohnsoncounteristhattheringcounter(

).

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isself-decodingApossiblesequencefora4-bitringcounteris(

).

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…1000,0100,0010…Adivide‐by‐N-counterisacounterthatgoesthrougharepeated

sequenceofNstates,anditisalsoknownasamodulo‐Ncounter.

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對Forcounterswithunusedstates,itisnecessarytoensurethatthecircuiteventuallygoesintooneofthevalidstatessothatitcanresumenormaloperation.

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對Fortransmission,datafromaUARTissentin

synchronousparallelform.

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錯Themaximummodulusofacounteris,

wherenisthenumberofstages(flip-flops)inthecounter.

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錯第七章測試StaticRAMis(

).

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volatileread/writememoryAnonvolatilememoryisonethat(

)

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retainsdatawithoutpowerappliedTheadvantageofdynamicRAMoverstaticRAMisthat(

).

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itissimplerandcheaperA4-bitparallel-in/parallel-outshiftregisterwillstoredatafor(

).

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1clockperiodWhendataisreadfromRAM,thememorylocationis(

).

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unchangedThefirststepinareadorwriteoperationforarandomaccessmemoryisto(

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placeavalidaddressontheaddressbusAddressmultiplexingcanreducethenumberofpinsintheICpackage.

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對OneofthemajorapplicationsofSRAMsisincachememoriesincomputers.

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對RAMisusedinacomputerto

storetheBIOS(BasicInput/Output

System.

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錯Memoryexpansion

isaccomplishedbyaddinganappropriatenumberofmemorychipstotheaddress,data,

andcontrolbuses.

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對第八章測試Thenumberofcomparatorsrequiredina10-bitflashADCis(

).

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1023Ifananti-aliasingfilterisnotusedindigitizingasignaltherecoveryprocess(

)

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ma