1、 Mentor Graphics Corp., 2005, Reuse by written permission only. All rights reserved.,HyperLynx 7.7 Update November 2006,Steve Kaufer Director of Engineering Bill Hargin Product Manager Steve McKinney Technical Marketing Engineer Pat Carrier Technical Marketing Engineer,HyperLynx,Productivity Easy to

2、 learn, use and deploy Minimizes design process impact Pre- and post-layout SI & EMC analysis, compatible with all major PCB tools Performance MHz to GHz analysis power and functionality Price Excellent return on investment makes it an every-desktop standard,Signal Integrity and EMC Analysis for Hig

3、h-Speed PCB Design,HyperLynx 7.7 Update,HyperLynx EXT HyperLynx GHz Design Kits Workshops Roadmap,v7.7 Status New EXT Features Major features planned for all Users,Analysis Major Oscilloscope improvements Batch-simulation improvements Automatic coupling of differential pairs Integration with Mentor

4、CTE/CES, for routing constraints in the Expedition PCB design flow IC Modeling Significant IBIS enhancements Series element and Model Selector support Major performance improvements for EBD-models IBIS v4.x support in Visual IBIS Editor REF/QPL model editor improvements,Oscilloscope Enhancements,Pro

5、bing Unlimited number of probes Ability to probe all SPICE ports Current probing Measurement Automatic measurement features Display Improved display of IC thresholds Flexible “area” zooming Ability to save/reload waveforms Optional export to Mentor Waveform Analyzer,Oscilloscope Enhancements,Batch-S

6、imulation Enhancements,Ease-of-use enhancements “Batch Auditor” step prior to simulation Driver edge times in nets spreadsheet Wildcard filtering in Nets spreadsheets Naming of net-level rules sets Suppression of crosstalk reporting within differential pairs Simulation enhancements New fast-driver /

7、 slow-receivers corner case Driver “round robin” for crosstalk simulations Net selection for Quick Analysis General improvements Generation of .XLS output files Log files with detailed settings for batch simulations,Batch-Simulation Enhancements,Automatic Coupling of Differential Pairs,The two halve

8、s of a differential pair automatically couple No need for user to adjust crosstalk thresholds,CTE/CES Integration,Integration with Mentor CTE/CES, for routing constraints: Offers a way for engineers to “record” results of LineSim simulations as PCB-routing constraints Creates a constraint template,

9、which can be edited within CTE / CES,REF/QPL Model Editor Enhancements,GUI improved to use a convenient spreadsheet Set resistor/capacitor “pack” style in editor,IBIS Enhancements,IBIS v4.x support in Visual IBIS Editor Integrates latest version of IBIS Open Forum parser/checker Supports IBIS 4.x ke

10、ywords For keyword highlighting in editor In “model-structure” pane EBD-model performance improvements Significantly improves performance of BoardSim for nets with unusually large or many EBD models More Series element and model selector support,IBIS Enhancements,Support for R Series and C Series ke

11、ywords Provides: On-die differential terminators Series R and C packs inside EBD models Support for Model Selector keyword Provides: Interactive selection of IBIS model variant in Assign Models GUI Control of the selected model for every pin referencing the Model Selector switches an entire bus at o

12、nce,DDR2 Signal Derating,Custom DDR2 oscilloscope controls will be released in Q4-2005,Signal analysis and timing requirements much more complicated than standard DDR,DDR2 Support,DDR2 support in HyperLynx On Die Termination Slew rate measurements Timing requirements and signal derating Typical Layo

13、ut Constraints Unbuffered DIMM architecture Pre-built simulation examples Differential clock topology Differential Strobe topology Data (DQ) topology,DDR2 Electrical Characteristics,Vil and Vih voltage levels depend on the speed grade Vref = 900 mV Used for setting up switching thresholds (Vih and V

14、il) Vih/Vil AC Thresholds = Vref +/- 250 mV for DDR2-400 & 533 = Vref +/- 200 mV for DDR2-667 & 800 Vih/Vil DC Thresholds =Vref +/- 125 mV for all DDR2,Vih ac,Vref,Vil ac,Vih dc,Vil dc,DDR2 Timing Characteristics,Setup flight time measurement Rising Edge Last crossing of Vref + DC Guard-band to firs

15、t crossing of Vih-ac Falling Edge Last crossing of Vref DC Guard-band to first crossing of Vil-ac Hold flight time measurement Rising Edge First crossing of Vil-dc to the first crossing of Vref AC Guard-band Falling Edge First crossing of Vih-dc to the first crossing of Vref + AC Guard-band,Vih ac,V

16、ref,Vil ac,Vih dc,Vil dc,Vref Guard-band,Vref + Guard-band,DDR2 Timing Characteristics,Signal derating required to meet setup and hold times Find nominal slew rate,Setup,Hold,DDR2 Timing Characteristics,Setup If any of the signal falls to the right of the nominal slew rate in the switching region, s

17、ignal must be derated,Hold If any of the signal falls to the left of the nominal slew rate in the switching region, signal must be derated,HyperLynx 7.7 Update,HyperLynx EXT HyperLynx GHz Design Kits Workshops Roadmap,v7.7 Status New GHz Features Major features planned for SERDES/high-freq. Users,An

18、alysis Fast eye diagrams Modeling ADMS integration (mixed SPICE/IBIS simulation) SPICE-modeling improvements (connectors, etc.) Padstack editing/modeling in LineSim Touchstone model viewer Touchstone model fitter (complex-pole fitting),Fast Eye Diagrams,Many orders of magnitude faster than time-doma

19、in simulation Highly accurate, unless channel is significantly non-linear Includes BER bathtub curve Can automatically generate the worst- case bit stimulus, for maximally closed eye Better than random PRBS stimulus,IC Modeling,ADMS Integration Gives users the ability to mix SPICE and IBIS models Un

20、like “Eldo for HyperLynx” Uses SimAPI module from ICX,Padstack Editing/Modeling in LineSim,Allows “what-if” vias to be created in LineSim New via symbols added to the free-form schematic editor Padstack editor allows full geometric description For single or differential vias Via properties dialog bo

21、x adds additional detail,Padstack Editing/Modeling in LineSim,Touchstone Model Viewer,Visually displays Touchstone models (S/Z/Y parameters), with . Magnitude Phase Real/imaginary Polar plot Passivity plot Runs checker for model causality and passivity Links to complex-pole fitter application, for f

22、itting and other “transformations” of model,Touchstone Model Viewer,Touchstone Model Fitter,Fits Touchstone models into a set of complex poles Poles can be simulated directly in Eldo Has many advantages over HSPICEs / Cadences Touchstone methods 10 times faster Huge Touchstone models are greatly com

23、pressed Results are guaranteed causal Models can also be passivated Much more accurate in long eye-diagram simulations No local-truncation error,SPICE Connector Modeling Enhancement,In a multi-board design, a .HYP file containing a connector can optionally omit the connector parasitics normally impo

24、sed by the multi-board wizard,HyperLynx 7.7 Update,HyperLynx EXT HyperLynx GHz Design Kits Workshops Roadmap,Technology Kits,DDR DDR2 PCIX PCI Express USB Serial ATA,SATA Transceiver,TX Testload,DDR Technology Kit,DDR Technology Overview Switch thresholds Supply voltages Timing requirements DIMM lay

25、out Typical Layout Constraints Unbuffered DIMM architecture Pre-built simulation examples Address, CMD, and Control net topology Data/Strobe net topology,Strobe,Data,DDR Technology Kit,LineSim FFS Topology,Address,Data,DDR2 Technology Kit,DDR Technology Overview On Die Termination Slew rate measurem

26、ents Timing requirements and signal derating Typical Layout Constraints Unbuffered DIMM architecture Pre-built simulation examples Differential clock topology Differential Strobe topology Data (DQ) topology,Memory Controller,DIMM Slot 1,DIMM Slot 2,Strobe,Data,DDR2 Technology Kit,LineSim FFS Topolog

27、y,Differential Clock,Data,Differential DQS,DDR2 Technology Kit,DDR2 Signal Derating,PCI-X Technology Kit,PCI-X Technology Overview Operation frequency Test loads Timing requirements Switching thresholds Common Design issues Design trade-offs between different topologies Pre-built simulation examples

28、 Tee topology Daisy Chain topology,PCI-X Technology Kit,LineSim FFS Topology,Mr. T,Daisy Chain,PCI Express Technology Kit,PCI Express Technology Overview Operating speeds and encoding Interconnect loss budget TX and RX eye masks Compliance test methodology Common Design issues Loss mechanisms Crosst

29、alk Pre-built simulation examples Identifying and controlling loss in different ways Forward and reverse crosstalk Effects of de-emphasis,PCI Express Technology Kit,LineSim FFS Topologies,PCI Express w/ crosstalk,PCI Express w/wo de-emphasis,PCI Express loss comparison,USB Technology Kit,USB Technol

30、ogy Overview Operating speeds Impedance requirements Flight time requirements Receive and Transmit eye masks Common Design issues Dealing with impedance discontinuities Pre-built simulation examples USB cable models and ribbon cable examples Built in USB 2.0 compliance test pattern,USB Technology Ki

31、t,LineSim FFS Topology,USB 2.0,Serial ATA Technology Kit,SATA Technology Overview Operating speeds Interconnect requirements TX and RX eye masks Compliance test points Common Design issues Loss mechanisms Crosstalk Pre-built simulation examples RX requirements with a test load Crosstalk aggressors,S

32、ATA Transmitter,SATA Test load,Board etch,Serial ATA Technology Kit,LineSim FFS Topology,SATA with crosstalk,New Virtex-4 Design Kits,Virtex-4 RocketIO technology New configuration menu Easy model setup Pre-emphasis at driver Equalization at receiver,HyperLynx Kit for Stratix GX,Altera Stratix GX De

33、sign Kit Stratix GX Transceivers With Eldo SPICE models Drivers with pre-emphasis SPICE Package models S-parameter connector models Receiver equalization,HyperLynx Kit for Stratix GX,LineSim FFS Topology,Receiver/Equalizer Input,Equalizer Output,Differential Pair,SPICE Package,Rx,Tx,SPICE Package,Ba

34、ckplane,Differential Pair,S-Param Conn,S-Param Conn,Technology Kits,Future Design Kits Planned FibreChannel Gigabit Ethernet SAS Considering . FSB SDRAM FBD RapidIO Hypertransport Infiniband,SATA Transceiver,TX Testload,HyperLynx 7.7 Update,HyperLynx EXT HyperLynx GHz Design Kits Workshops Roadmap,A

35、vailable High-Speed Workshops,High-Speed Fundamentals Fundamentals of High-Speed Design (8 hours) HyperLynx Overview (4 hours) Hot Technologies SERDES Design Workshop (5 hours) DDR/DDR2 Workshop (5 hours) Hot Technology Workshop (8 hours) IC Modeling IBIS IC Modeling Workshop (4 hours and 8 hours),H

36、yperLynx 7.7 Update,HyperLynx EXT HyperLynx GHz Design Kits Workshops Roadmap,HyperLynx Product Roadmap,HyperLynx Thermal,HyperLynx Planner,HyperLynx EXT,HyperLynx GHz,HyperLynx PI,HyperLynx CLK,HyperLynx Expert,SHIPPING,IN DEVELOPMENT,FUTURES,2003,2008,v7.x: HyperLynx CLK,Exploration schematic and

37、spreadsheet-based interface that supports: Common-clock Source-synchronous Embedded-clock designs Avoids tedious, exhaustive timing analysis that most hardware engineers prefer to avoid,v8.0: HyperLynx PI,The feature set will be an evolutionary path spread over several releases Details are still bei

38、ng finalized Decoupling caps will be accounted for, including on-the-fly decoupling-cap planning Delta-I noise injected between planes by vias, and via coupling Ground bounce analysis based on “current spike” models Plane resonance analysis Detailed electromagnetic analysis of splits, including curr

39、ent returns,8.0 . . . 8.x,v8.x: HyperLynx PI, Contd.,Bypass/decoupling analysis The suitability of a set of decoupling capacitors for “bypassing” a PCBs power/ground planes and successfully providing local power to critical ICs, accounting for the capacitors values and positions,v8.x: HyperLynx PI,

40、Contd.,Via noise and crosstalk The interactions between vias and power/ground planes Including the generation of noise between plane pairs when high-speed signals pass through them on vias And including the effects on signal-carrying vias of nearby bypass capacitors and “stitching” vias,v8.x: HyperLynx PI, Contd.,Ground bounce, or “SSN” The amount of