1、第二章,CPLD/FPGA使用方法 AHDL語言 AHDL實驗設(shè)計,可編程邏輯器件的選擇,CPLD , FPGA or ASIC? 容量 宏單元數(shù)，邏輯單元數(shù) 寄存器數(shù)，門數(shù) 存儲器大小 速度 Tpd 可用管腳數(shù) 固定輸入管腳，可定義輸入/輸出管腳 工作電壓 電源電壓 接口電壓 功耗 封裝形式 配置方式 一次編程OTP ( One Time Programmable) 可再編程( Re-Programmable) 保持型，ISP 上電加載型，需要外置 EPROM,Selection of CPLD or FPGA,If circuit having a lot of combinatorial

2、 logic, use CPLD If circuit having a lot of Register logic, use FPGA,100% combinatorial logic 0% Register,0% combinatorial logic 100% Register,CPLD,FPGA,cont.,Select CPLD or FPGA depends on the circuit application CPLD for Combinatorial Logic Register Logic FPGA for Register Logic Combinatorial Logi

3、c Gate count need CPLD gate count is smaller than FPGA Speed Grade CPLD having less pin to pin I/O delay CPLD in general run faster than FPGA Memory need FPGA support Memory Price in general FPGA is lower in cost than CPLD,Select Guide,MAX 7000S Family Members,Feature,Usable gates,Macrocells,Max Use

4、r I/O,tPD (ns),fcnt (MHz),7032/S,600,32,36,5,178.6,7064/S,1,250,64,68,6,151.5,7096,1,800,96,76,6,151.5,7128/S,2,500,128,100,7.5,125,7160/S,3,200,160,104,7.5,125,7192/S,3,750,192,124,10,100,7256/S,5,000,256,164,10,100,FLEX 10K Family Members,Multi-volt System Guideline,Both CPLD and FPGA from Altera

5、support Multi-volt system interface Couple suggestion when doing Mulit-volt design 5V device, use 70000S/10K/6K/8KA/9K 3.3V device, use 7000A/10KA/10KV/6KA/9KA 2.5V device, use 7000B/10KE,cont.,VCCINT,GNDINT,Core,VCCIO,GNDIO,VCCIO,GNDIO,cont.,5.0-V Devices with MultiVolt Interface,(1) Input of Devic

6、e Driven by Altera Device Output Must Have 5.0-V Tolerance. (2) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance. (3) Use Open-drain outputs with pull-up to 5.0V.,Applicable Devices: FLEX10K, FLEX6000, FLEX8000, MAX7000/S, MAX9000/A,Note: For some of the smaller packages, the

7、re are no VCCIO pins, and therefore does not support Multi-volt interface.,3.3-V Devices with MultiVolt Interface I,(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance. (2) Use Open-drain outputs with pull-up to 5.0-V.,Applicable Devices: FLEX10KA, FLEX6000A, MAX7000A,Import

8、ant: Do not tie the VCCIO of these devices to 5.0-V power source. This will damage our devices.,3.3-V Devices with MultiVolt Interface II,(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance. (2) Use Open-drain outputs with pull-up to 5.0-V.,Applicable Devices: FLEX10KV, EPF8

9、282AV, EPM7032V,Important: Do not tie the VCCIO of these devices to 5.0-V or 2.5-V power source. This will damage our devices.,2.5-V Devices with MultiVolt Interface,(1) Input of Device Driven by Altera Device Output Must Have 3.3-V Tolerance. (2) Use Open-drain outputs with pull-up to 5.0-V.,Applic

10、able Devices: FLEX10KE, FLEX10KB,Packaging Considerations,Engineering Pin Count Board Space Efficiency Pin Compatibility with Other Devices Easy Prototype Development Manufacturing Board Space Efficiency PCB Trace Width Requirements Compatibility with Solder Reflow Process Quality / Yield / Cost,84

11、100 160 208 240 304 100 144 256 356 600 100 256 484 672,1.4 0.6 1.5 1.5 1.9 2.9 0.4 0.8 1.1 1.9 3.1 0.2 0.4 0.8 1.1,60 160 100 140 120 100 250 200 200 180 190 500 600 600 600,Packaging Metrics,PLCC PQFP (RQFP) TQFP Standard BGA (1.27-mm Pitch) FineLine BGA (1.0-mm Pitch),1.27 0.65 0.65 0.50 0.50 0.5

12、0 0.50 0.50 1.27 1.27 1.27 1.00 1.00 1.00 1.00,29 x 29 14 x 23 28 x 28 28 x 28 32 x 32 40 x 40 14 x 14 20 x 20 27 x 27 35 x 35 45 x 45 11 x 11 17 x 17 23 x 23 27 x 27,Pin Count,Board Area (in2),Pin Density (Pins/in2),Lead/Ball Pitch (mm),Body Size (mm),Package Type,Declining Usage,PQFP TQFP TQFP PQF

13、P Standard BGA Standard BGA,TQFP MicroBGA TQFP FineLine BGA Standard BGA FineLine BGA FineLine BGA,PDIP PLCC PQFP PGA PGA, Greater than or equal to : = Less than : highest_level = B”0100”; when 1 = highest_level = B”0010”; when others = highest_level = B”0001”; end case; end;,Bus Operation,SUBDESIGN

14、 decode1 ( a3.0, b3.0 : input; out3.0 : output; ) begin out0 = a0 ,More on Bus Operation,Bus Operation a9.0, b9.0 a = b; a7.4 = b9.6; a9.8 = VCC; a9.8 = 1; a9.8 = 2; a9.8 = 3; a3.0 = GND a3.0 = 0; temp = b0 a2.1 = temp,a7=b9, a6=b8, a5=b7, a4=b6 %,a9.8 connect to VCC,a9.8 = B”01”,a9.8 = B”10”,a9.8 =

15、 B”11”,a3.0 connect to GND,a3.0 = B”0000”,a2 = temp, a1 = temp,Advance Bus Operation,Bus b3.0 b3, b2, b1, b0 (having 4 members) MSB is b3, LSB is b0 ARRAY BUS a3.02.0 a3_2, a3_1, a3_0, a2_2, a2_1, a2_0, a1_2, a1_1, a1_0, a0_2, a0_1, a0_0 (having 12 members) MSB is a3_2, LSB is a0_0,Tri-state Buffer,

16、SUBDESIGN tri_state (a, enable : input; b : output;) begin b = tri(a, enable); end;,SUBDESIGN tri_state ( a, enable : input; b : output;) variable temp : tri; begin temp.in = a; temp.oe = enable; b = temp.out; end;,時序電路的設(shè)計,Register DFFE (D-FF with enable) TFF/TFFE JKFF/JKFFE SRFF/SRFFE Counter Use “

17、Clock Enable”,Register Logic,SUBDESIGN flip_flop ( d, clk : input; q : output;) begin q = dff(d,clk, ,); end;,Register Buses,SUBDESIGN bus_reg ( clk, d7.0 : input; q7.0 : output; ) variable ff7.0 : dff; begin ff.clk = clk; ff.d = d; q = ff.q; end;,Design 8 bits Counter is Easy,SUBDESIGN 8bits (clk :

18、 input; q7.0 : output; ) variable temp7.0 : dff; begin temp.clk = clk; temp.d = temp.q +1 ; q = temp.q; end;,9-bit up/down counter with load and enable,SUBDESIGN ahdlcnt ( clk, ld, en, clr, up/down, d8.0 :INPUT; q8.0 :OUTPUT; ) VARIABLE count8.0 :DFF;,BEGIN count.clk = clk; count.clrn = !clr; IF ld

19、THEN count = d; ELSIF en THEN IF up/down THEN count = count + 1; ELSE count = count - 1; ENDIF; ELSE count = count; END IF; q = count; END;,Clock Enable,If you wish to load a register on a specific rising edge of the global Clock, Altera recommends that you use the Clock Enable input of one of the D

20、FFE, TFFE, JKFFE, or SRFFE Enable-type flipflops to control when the register is loaded.,Reg_ctrl3.0.d =DB3.0; Reg_ctrl3.0.clk = niow; Reg_ctrl3.0.ena= cs;,Reg_ctrl3.0.d =DB3.0; Reg_ctrl3.0.clk = niow,State Machine,SUBDESIGN simple ( clk, reset, jump : input; q : output; ) variable ss : MACHINE WITH

21、 STATES (S0,S1); begin ss.clk = clk; ss.reset = reset; case ss is when s0 = q = gnd; if (jump) then ss = s1; end if; when s1 = q = vcc; if (jump) then ss = s0; end if; end case; end;,State Machine Diagram,Note : All State Machine Variable must be associated with a CLOCK,jump=1,jump=1,q = 0,q = 1,jum

22、p=0,jump=0,狀態(tài)機仿真波形,State Machine (2),SUBDESIGN stepper ( reset, ccw, cw, clk : input; phase3.0 : output;) variable ss : MACHINE OF BITS (temp3.0) WITH STATES ( s0 = B”0001”, s1 = B”0010”, s2 = B”0100”, s3 = B”1000”); begin ss.clk = clk; if (reset) then ss = s2; end if; phase = temp;,TABLE ss, ccw, c

23、w = ss; s0, 1, x = s3; s0, x, 1 = s1; s1, 1, x = s0; s1, x, 1 = s2; s2, 1, x = s1; s2, x, 1 = s3; s3, 1, x = s2; s3, x, 1 = s0; END TABLE; end;,仿真波形,State Machine without Recover State,SUBDESIGN recover ( clk, go : input; ok : output;) variable sequence : MACHINE OF BITS (q2.0) with STATES ( idle, o

24、ne, two, three, four, illegal1, illegal2, illegal3); begin sequence.clk = clk; case sequence is when idle = if (go) then sequence = one; end if; when one = sequence = two; when two = sequence = three; when three = sequence = four; end case; ok = (sequence = four); end;,Better have Recover within Sta

25、te Machine,SUBDESIGN recover ( clk, go : input; ok : output;) variable sequence : MACHINE OF BITS (q2.0) with STATES ( idle, one, two, three, four, illegal1, illegal2, illegal3); begin sequence.clk = clk; case sequence is when idle = if (go) then sequence = one; end if; when one = sequence = two; wh

26、en two = sequence = three; when three = sequence = four; when OTHERS = sequence = idle; end case; ok = (sequence = four); end;,層次化的設(shè)計方法-模塊的調(diào)用,VARIABLE counter : 4count; decoder : 16dmux; BEGIN counter.clk = clk; counter.dnup = GND; decoder.(d,c,b,a) = counter.(qd,qc,qb,qa); out15.0 = decoder.q15.0; END;,INCLUDE