1、鋁柵、硅柵器件的版圖,鋁柵工藝MOSFET的結(jié)構(gòu)Structure,Gate,Source,Drain,N阱硅柵CMOS IC的剖面圖,以SiO2為柵介質(zhì)時(shí)，叫MOS器件，這是最常使用的器件形式。歷史上也出現(xiàn)過(guò)以Al2O3為柵介質(zhì)的MAS器件和以 Si3N4為柵介質(zhì)的MNS 器件，以及以SiO2+Si3N4為柵介質(zhì)的MNOS器件，統(tǒng)稱為金屬-絕緣柵-半導(dǎo)體器件-MIS 器件。 以Al為柵電極時(shí)，稱鋁柵器件。以重?fù)诫s多晶硅(Poly-Si) 為柵電極時(shí)， 稱硅柵器件。它是當(dāng)前MOS器件的主流器件。,硅柵工藝是利用重?fù)诫s的多晶硅來(lái)代替鋁做為MOS管的柵電極，使MOS電路特性得到很大改善，它使|VT

2、P|下降1.1V，也容易獲得合適的VTN值并能提高開(kāi)關(guān)速度和集成度。硅柵工藝具有自對(duì)準(zhǔn)作用，這是由于硅具有耐高溫的性質(zhì)。柵電極，更確切的說(shuō)是在柵電極下面的介質(zhì)層，是限定源、漏擴(kuò)散區(qū)邊界的擴(kuò)散掩膜，使柵區(qū)與源、漏交迭的密勒電容大大減小，也使其它寄生電容減小，使器件的頻率特性得到提高。另外，在源、漏擴(kuò)散之前進(jìn)行柵氧化，也意味著可得到淺結(jié)。,鋁柵工藝為了保證柵金屬與漏極鋁引線之間有一定的間隔，要求漏擴(kuò)散區(qū)面積要大些。而在硅柵工藝中覆蓋源漏極的鋁引線可重迭到柵區(qū)，這是因?yàn)橛幸唤^緣層將柵區(qū)與源漏極引線隔開(kāi)，從而可使結(jié)面積減少30%40%。硅柵工藝還可提高集成度，這不僅是因?yàn)閿U(kuò)散自對(duì)準(zhǔn)作用可使單元面積大為

3、縮小，而且因?yàn)楣钖殴に嚳梢允褂谩岸影氩季€”即一層鋁布線，一層重?fù)诫s多晶硅布線，一層重?fù)诫s的擴(kuò)散層布線。由于在制作擴(kuò)散層時(shí)，多晶硅要起掩膜作用，所以擴(kuò)散層不能與多晶硅層交叉，故稱為兩層半布線鋁柵工藝只有兩層布線：一層鋁布線，一層擴(kuò)散層布線。硅柵工藝由于有兩層半布線，既可使芯片面積比鋁柵縮小50%又可增加布線靈活性。,簡(jiǎn)化N阱硅柵CMOS工藝演示,氧化層生長(zhǎng),曝光,氧化層的刻蝕,光刻1，刻N(yùn)阱掩膜版,N阱注入,光刻1，刻N(yùn)阱掩膜版,形成N阱,氮化硅的刻蝕,N阱,P-SUB,場(chǎng)氧的生長(zhǎng),N阱,P-SUB,去除氮化硅,N阱,P-SUB,重新生長(zhǎng)二氧化硅（柵氧）,N阱,P-SUB,生長(zhǎng)多晶硅,N阱,P

4、-SUB,刻蝕多晶硅,N阱,P-SUB,刻蝕多晶硅,N阱,P-SUB,場(chǎng)氧化層,柵氧化層,P+離子注入,N阱,P-SUB,N+離子注入,N阱,P-SUB,生長(zhǎng)磷硅玻璃PSG,N阱,P-SUB,光刻接觸孔,N阱,P-SUB,刻鋁,N阱,P-SUB,刻鋁,N阱,P-SUB,N阱,P-SUB,鋁柵PMOSFET的制造流程,Step 0: Start with a bare n-type silicon wafer.,N Doped Silicon,*Step 1: (layering) Grow thick layer (5000) of silicon dioxide (field oxide)

5、to act as a doping barrier.,*Step 2a: (patterning) Apply photoresist.,Source/Drain: Photomask (dark field) mask 1,Clear Glass,Chromium,Cross Section,Step 2b: (patterning) Expose photoresist to create temporary pattern for source/drain regions.,N Doped Silicon,Thick Field Oxide,Photoresist,Ultraviole

6、t Light,Photomask,Step 2c: (patterning) Develop photoresist, completing temporary pattern for source/drain regions.,N Doped Silicon,Thick Field Oxide,Photoresist,Step 2d: (patterning) Wet etch permanent openings for source/drain into field oxide.,N Doped Silicon,Thick Field Oxide,Photoresist,Step 2e

7、: (patterning) Remove photoresist. Permanent pattern remains in the silicon dioxide.,N Doped Silicon,Thick Field Oxide,Source/Drain Windows: Microscope View mask 1,Bare Silicon,Thick Field Oxide,Cross Section,*Step 3a: (doping) Apply p-type spin-on dopant film. Boron penetrates into the silicon thro

8、ugh the holes in the field oxide to begin formation of the source and drain regions.,N Doped Silicon,P+ Drain,P+ Source,Thick Field Oxide,Boron-Doped Spin-On Oxide,Step 3b: (heat treatment) Drive dopants deeper into silicon using high temperatures (1000), completing formation of the source and drain

9、 regions.,N Doped Silicon,P+ Drain,P+ Source,Thick Field Oxide,Boron-Doped Spin-On Oxide,P+ Drain,P+ Source,Channel Length - Leff,Step 4a: (layering) Wet etch to remove SOD (spin-on dopant) and field oxide layers.,N Doped Silicon,P+ Drain,P+ Source,Source/Drain Doping: Microscope View Mask1,P+ Doped

10、 Source and Drain (not actually visible),N-Doped Substrate,Cross Section,*Step 4b: (layering) Regrow new field oxide layer.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Oxide grows slightly thicker over doped areas.,*Step 5a: (patterning) Apply photoresist.,Thick Field Oxide,N Doped Silicon,

11、P+ Drain,P+ Source,Photoresist,Gate: Photomask (dark field) mask2,Clear Glass,Chromium,Cross Section,Step 5b: (patterning) Expose photoresist to create temporary pattern for gate region.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Ultraviolet Light,Photomask,Step 5c: (patterning

12、) Develop photoresist, completing temporary pattern for gate region.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Step 5d: (patterning) Wet etch permanent opening for gate region into field oxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Photoresist,Step 5e: (patterni

13、ng) Remove photoresist. Permanent pattern remains in the silicon dioxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,*Step 6: (layering) Grow thin layer (700) of silicon dioxide to act as the gate oxide for the transistor.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxid

14、e,After Gate Oxide Growth: Microscope View,P+ Doped Source and Drain (under Field Oxide),Thick Field Oxide,Thin Gate Oxide,Cross Section,*Step 7a: (patterning) Apply photoresist.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7b: (patterning) Expose photoresist

15、 to create temporary pattern for contact holes.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Ultraviolet Light,Photomask,Contacts: Photomask (dark field) mask 3,Clear Glass,Chromium,Cross Section,Step 7c: (patterning) Develop photoresist, completing temporary patt

16、ern for contact holes.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7d: (patterning) Etch permanent holes for contacts into field oxide.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 7e: (patterning) Remove photoresist.

17、 Permanent contact holes in the field oxide remain.,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,After Contact Patterning: Microscope View,Contact Hole (bare silicon),P+ Doped Source and Drain (under Field Oxide),Thick Field Oxide,Thin Gate Oxide,Cross Section,*Step 8a: (laye

18、ring) Deposit aluminum layer over entire wafer surface.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Step 8b: (heat treatment) Alloy aluminum at moderate temperatures (450) to form good electrical contact with silicon.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+

19、 Source,Thin Gate Oxide,Alloyed Aluminum-Silicon,*Step 9a: (patterning) Apply photoresist.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Step 9b: (patterning) Expose resist to create temporary pattern to define metal interconnects and gate electrode.,Metal,Thick Field Oxide,N Doped Silicon,P+ Drain,P+ Source,Thin Gate Oxide,Photoresist,Ultraviolet Light,Photomask,Metal Interconnects: Photomask (light field),Chromium,Clear Glass,Cross Section,Step 9c: (patterning) Develop photore