第十二章后端設計第十二章后端設計OutlinesBackendDesignFlowFloorplanPlace&RoutePhysicalVerificationSignalIntegrityDFM/DFYOutlinesBackendDesignFlowStepsofBackend/PhysicalDesignSynthesisFloorPlanningPlacementScanchaininsertionandre-ordering(optional)ClockTreeSynthesisRoutingParasiticandnetlistextractionPoweranalysisSignalintegritycheckingFinaltiminganalysis(STAandsimulation)ECO(optional)LVS/DRCExportGDSIILVS/DRCusingsign-offtoolsStepsofBackend/PhysicalDesBackendFlowwithECOEngineeringChangeOrder(ECO)Achievedbyaddingsmallamountofcellsinlimitedarea,sizingbuffersandroutingtheconnectionsPreventdisturbingtheplacementandroutingoftherestofthechipBackendFlowwithECOEngineerKeepinmind:

Performance,Power,Size,ReliabilityItisnotimpossibletodevelop“plug&Play”toolsKeepinmind:FloorplanningBasedonnetlist,createareasoffunctionalityonyourchipDeterminetheplacementofblocksDeterminetheplacementofI/OpinsDeterminethepowersupplystrategyGivefeedbackonhoweasyyourfloorplanmightbetowire(Globalrouting)andhowbigthechipisFloorplanningBasedonnetlist,ChipFloorplanningConsiderationsChiplevelfloorplanningHighspeedblockissueLocationaffectthetimingperformanceAnalogblockissuecleanVdd/Vss;minimalspacingtodigitalblock;IOlocationDiesizeissuePinlimited;CorelimitedPower-GroundroutingissuePowerringwidthaccordingtopoweranalysisPowerstrip/meshspacingPinplacementandIOringissue(willbetalkedinnextclass)Padpitchvs.boundingrule;ESD;noiseisolation;ChipFloorplanningConsideratiDieSizeIssue–cont.Determinetheareaforstandardcells“Utilization”–70%?80%?90%?ExtraspaceforclktreesynthesisExtraspaceforscanchainLayersforroutingDieSizeIssue–cont.DetermineHardMacroPlacementMacrosaregenerallyplacedaroundtheperipheralI/Oring

Acontiguousareaforstandardcells.Higherfreedomforyourplace-and-routetoolsduringplacementandroutingofthestandardcellsThegoalofmacroplacementisto:Reducetiming-criticalpathsbetweenthemacrosandinterfacinglogic. Reduceinterconnectionsinthefollowingorder:ChipI/OtomacrosMacrotomacroMacrotostandardcellblocksHardMacroPlacementMacrosarePower/GroundDevelopmentIRDropandElectromigrationPower-netIRdropdegradesthesupplyvoltagelevelExcessivecurrentdensityinmetalwirecauseselectromigrationfailurewhichbreaksmetalconnectionMoresignificantIRdropeffectwhenVddgetssmallerHighercurrentdensitywhenmetalwirewidthissmallerPower/GroundDevelopmentIRDroPower/GroundDevelopment-cont.RingstructurePowerringsaroundalllayoutblocksMajorpowertrunksbetweenlayoutblocksDifficulttoguaranteetheworstIRdropStrapstructureSimple,easyforroutingMeshstructureEvenlydistributeofIRSpacingofPowerstripsconsideration

IRdropanalysisFixtheprobleminearlystageP/GStructuresPower/GroundDevelopment-cont.BeWareofMaximumWidthRuleMaximumwirewidthlimitduetothermalstressandlocaldensityrulesSlottingvs.“bus”ofthinwiresDisadvantageofslotting:SlotsmaynotbealignedwithcurrentflowTrueIRdropnotknownuntilafterslottingEspecialhappenforPower/GroundringsM1M1VS.GNDGNDGNDGNDCommonlyusedforpower/groundBeWareofMaximumWidthRuleMPlacementBasedonagivenfloorplan,determinethelocationofcellsinagivennetlistGoals&objectivesRoutabilityGuaranteetheroutercancompletetheroutingstep(Globalrouting)TimingMinimizeallcriticalnetdelaysMinimizediesizeMakethechipasdenseaspossibleSignalIntegrityPlacementBasedonagivenfloCheckfeasibilityofroutingafterplacementLogiceffort-forthosepathswithpositiveslack,reducecellsizeCongestionandFixBeforeAfterCongestionareasCheckfeasibilityofroutingaRoutingCompletepower/ground/clockrouting(clocktreesynthesis)Completedetailedwirerouting,conformwiringruleandorder)ImprovethedensityMinimizethelayerchangesImprovecriticalpathandmeettimingrequirementProducearouteddesignfreeofDRC/LVSviolationsRoutingCompletepower/ground/cGeneralRoutingFlowClockTreeSynthesisAddbuffers/inverters,minimizeclkskewanddelayPostPlacementOptimization(PPO)FixsetupviolationPre-RouteStandardCellsVDD/VSSrailsonmetal1VerifyPGconnectionandroutingRouteGroupNetclocksbusroutingPost-RouteCTOFixclkskewandinsertiondelayGlobalRoutingcriticalpathlongwire,interconnectionGeneralRoutingFlowClockTreRoutingflow–cont.TrackAssignment&DetailRoutingWireconnectionSearch&Repair(DRC/LVS)fixroutingviolation(unconnectednets,shorts)PostRouteOptimizationFixtimingCoarseLVS&DRCcheckingmetalwidth,notch&gapcheckingDataOutputstreamout:gds2formatverilogout:hierarchy(PT)/non-hierarchy(forHercules)parasiticout:spefformat(cellview)Routingflow–cont.ClockTreeSynthesisObjective:minimizeclockskewoptimizeclockbuffersClockTreeSynthesisObjectiveBasicCTSFlow

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Concepts

BasicCTSFlow

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ConceptsClockConstraintDefine:Clksource:rootpin,targetinsertiondelay,targettransitiontimeatclkportClkendpoint:Synchronouspin,ignore/excludepinDrivingcell,clkcell,delaycell:buffers,inverters,specialclkcellsDRC:maximumtransitiondelay,maximumnetcapacitance,maximumfanout,clknumberofbufferlevelsClockConstraintDefine:ClockSkewGlobalSkewandLocalSkewGlobalskewGlobalskewistheclockarrivaltimedifferencebetweenanytwoflip-flops.LocalskewLocalskewistheclockarrivaltimedifferencebetweentwoflip-flopsthatareadjacentthroughcombinationallogic.ClockSkewGlobalSkewandLocConceptofUsefulSkewUsefulskewisamethodofintentionallyskewingaclocktoimprovethetimingonacircuit.ItisalsocommonlyusedinECOWarning:Couldcauseproblemin

DFTscaninsertion

ConceptofUsefulSkewUsefulsUseCTSforHigh-FanoutNetSynthesisHigh-fanoutpins:rest,scan_enNeedtobalancehigh-fanoutpinstoguaranteethefunctionalityUsingCTStool:high-fanoutnetsbyinsertingabalancedbuffertreeTominimizebothskewandinsertiondelayButshouldavoidusinglargebuffersforpowersavingUseCTSforHigh-FanoutNetSyLargeSoCClockDistributionPartitionthedesigntoseveralblocksCTSforeachblockClktreenetworkattoplevelExternalclockIPCore

orModuleCoreInternalClockNetPLLGlobalClockNetLargeSoCClockDistributionPaHTreeforTopClockNetworkUsebigbuffertobalancedelayandclkskewEqualdistance,equalloads,equaldrivingabilityHTreeforTopClockNetworkUsClockDistributionCaseStudy:Pentium?SpinesKurdetal.,AmultigigahertzclockingschemeforthePentium?4microprocessor,JSSC2001ClockDistributionCaseStudy:ClockDistributionCaseStudy:

Intel’sItanium?HTreeClockingTametal.,ClockgenerationanddistributionforthefirstIA-64microprocessor,JSSC2000ClockDistributionCaseStudy:IssuesLargeamountofclockbuffersaddedonclocktreePowerconsumptionNoisetosupplylinesReducepowerconsumptionWidewirewidthsClockgatingcellplacementLimitationofusinglargeclockbuffercellsReducenoiseSpecialclockbuffercellswithdecouplingcapacitorIssuesLargeamountofclockbuExtractionWhencompletedetailedrouteWriteoutthehierarchicalnetlistandparasiticforbackannotationDatamanagementonhugefileofextractedparasiticdataAccurateRCandtimingmodelfornanometerdesignWidthandspacingdependenceResistanceshieldingLocaldensityeffectExtractionWhencompletedetailSDFBackAnnotationUsedincell-baseddesignflowPerformsdelaycalculationonparasiticRCsininterconnectwiresDSPF-DetailedStandardParasiticFormatSPEF–StandardParasiticexchangeFormatSDF-StandardDelayFormatusedforpost-layoutsimulationCanbeconvertfromPrimeTimeSDFBackAnnotationUsedincelPhysicalVerificationDRC-DesignRulecheckVerifythemanufacturingrules,example:InternallayerchecksWidemetalchecksMetalslottingneededforwidemetalLayer-to-layerchecksDFM/DFYExample:AntennaRuleCheckLVS–Layoutvs.SchematicsComparelayouttoschematics-everycellandnetPhysicalVerificationDRC-DeDRCTrendsandChallenge>75%timeonmetallayerandviacheckERC-typechecksincreasingRiseofpre-tapeoutDFMutilitiesDRCTrendsandChallenge>75%tLVSLayoutvs.Schematic(LVS)CheckphysicallayoutagainstfunctionalgatelevelschematictoensureallintendedconnectivityhasbeenmaintainedSteps:Extractthenetlistfromlayout(GDSII)ComparethenetlistwiththeoneafterroutingandoptimizationHints:

MostofLVSerrorsarecausedbymanuallayoutorcongestion“Virtualconnect”(connectedbytext)couldcauseakillerfailureLVSLayoutvs.Schematic(LVS)SignalIntegritySignalIntegrityistheabilityofasignaltogeneratecorrectresponseinacircuitSignalhasdigitallevelsatappropriateandrequiredvoltagelevelsatrequiredinstantsoftimeCrosstalk,IRDrop,ElectromigrationSignalIntegritySignalIntegriLayoutParasiticvs.CircuitPerformanceInterconnectparasiticresistors,capacitorsandinductorscauseextratimingdelayAdditionalpowerconsumptioncausedbyparasiticRCInter-wirecapacitancescausecouplingnoiseandwilldominateinterconnectwiredelaysParasiticresistancesinpowersupplycausevoltagedropandmaydegradecircuitperformanceHighercurrentdensityinpowernetmaycauseelectromigrationfailureLayoutParasiticvs.CircuitPInductanceEffectsInductivecouplingeffectissignificantforlonginterconnectsandforveryfastsignaledgerateInductivecouplingisnegligibleatshorttraceinterconnects,sincetheedgetraceislongcomparedtotheflighttimeofthesignalInductanceextractionandsimulationaremoredifficultthancapacitanceCLInductanceEffectsInductivecoCrosstalkAnalysisDefinitionAggressor:generatingcrosstalkVictim:receivingcrosstalkTimingsensitiveCrosstalkanalysisconsistingsignaltransitiontimingwindowcaneliminatepessimisticdelaycalculationThecrosstalkspikeisrelatedtocapacitancevalueandthevictimdriverimpedanceCrosstalkAnalysisDefinitionCrosstalkAnalysis–cont.TimingsensitiveCrosstalkAnalysis–cont.TimiCrosstalkPreventionPreventcrosstalkfromsynthesisstageMinimizethedrivingsizeonthosenon-criticalpathtoreducethenumberofaggressorsApplymaxtransitiontime(set_max_transition)inphysicalsynthesis/placementtoavoidlongnetsCrosstalkPreventionPreventcrCrosstalkPrevention–cont.FromroutingstageEffectivespacingbetweennoiseregionandquiteregionShieldingbetweencriticalpathsCrosstalkPrevention–cont.FrCrosstalkPrevention–cont.Fromroutingstage–cont.BufferinsertionInsertedbufferbreaksupthecouplingcapacitanceoflongwireCrosstalkPrevention–cont.FrCrosstalkPrevention–cont.Fromroutingstage–cont.BuffersizingIncreasethedriversizeofvictimDecreasethedriversizeofaggressorTrackreorderingTrackreorderingisbasedontimingwindowCrosstalkPrevention–cont.FrCrosstalkPrevention–cont.ForinductancecrosstalkCoplanarShieldsReferencePlanStaggerInverter/BufferCrosstalkPrevention–cont.FoElectromigrationEffectsTheelectronsflowthroughthewiresandcollidew/metalatoms,producingaforcethatcausesthewirestobreakCausedbythehighcurrentdensitiesandhighfrequenciesgoingthroughthelong,verythinmetalwiresMTTF(MeanTimeToFailure)increaseswhencurrentdensityandtemperatureincreaseCanbeeliminatedbyusingtheappropriatewiresizingElectromigrationEffectsTheelFixEMControllingcurrentdensitytolimitelectromigrationfailureisneededindesignandverificationLayoutoptimization:Increasethepowerlinewidth,layerIncreasethepowerpadsIncreasetheconnectionIssuesMoremetal(add8%costperlayer)Larger,slowerdesigns(growinxandy)FixEMControllingcurrentdeOtherConsiderationsESD(willbetalkedinnextclass)Packagevs.performance(willbetalkedinnextclass)DFM/DFYOtherConsiderationsESD(willDFM/DFY90nmandbelowtechnologieschallengesinyieldDFM–DesignforManufacturabilityDFY–DesignforYieldDFM/DFY90nmandbelowtechnoloDFMandDFYDFMisthemanagementoftechnologyconstraints(sizingrules)appliedtothelayoutAmanufacturabledesignhoweverisnotnecessarilyahigh-robustorhigh-yieldingdesign.DFY,aspartofDesignforManufacturability,concentratesonthedevelopmentandqualityofthecircuitdesigninthepre-andpost-layoutphase.DFYisthemanagementofdesignsensitivitiestothemanufacturingprocessandhelpstoguaranteehigh-yieldingdevicesDFMandDFYDFMisthemanagemeDFM/DFYMethodologyOptimalresolutionenhancementtechnology(RET)MaskandexposureOpticalProximitycorrection(OPC)PhaseShaftMask(PSM)YieldenhancementandoptimizationtechnologyDFMrulesimplementationToovercomelimitsofOPCYieldcheckingduringthelayoutstageSupportedbyEDAtoolsDFM/DFYMethodologyOptimalresWhyNeedRET?WavelengthusedvsprocessgenerationWhyNeedRET?WavelengthusedvDesignforManufacturingNotallthethingscanbedonebymaskandexposure:CorrectionsarenotcompleteSomedesignscannotbebuiltatallwithcertainRETtechnologiesOfthosethatCANbebuilt,somearemoremanufacturableafterRETthanothersDFM/DFY-drivenroutingOPC-drivenroutingPSC-drivenplacementDFMruleimplementationDesignforManufacturingNotaDFM/YRulesLimittheuseofminimalpoly-enclosedgates,minimallyenclosedviasandsinglycontactedlinesBetteryieldLessresistanceExample:ViaVoidrules-doubledviasDFM/YRulesLimittheuseofmiCurrentDFM/YDesignFlowSupportedLoadDesignPerformantenna

fixesAddcontacts/viaMetalFill&SlottingVerifyLVSandDRCCurrentDFM/YDesignFlowSuppWhyNeedDoubleVias?CopperprocessingcausesnewproblemsforviasVoidsinCumigrateunderthermalstresstowardsviasIfenoughvoidsmigratetoaviaitcancausefailureWorseat90/65nmduetoincreasedstressofsmallerviaVoidscanmigratelongdistances~10micronsVoidscanmigratearoundcornersWhyNeedDoubleVias?CopperprYieldvs.AreaYieldvs.AreaAntennaRulesAntennaruleshavenothingtodowithtraditionaldefinitionofantennaReallyacollectorofstaticcharge,notelectromagneticradiationAntennaproblemonlyhappensduringmanufacturingPlasma-basedprocessforetching,oxidedepositionPlasmaetcherincludeavoltageintofl