1、DDR3 簡介/調(diào)試,Kade Huang 2013.1,DDR/DDR2/DDR3比較,DDR2/DDR3 比較之PIN腳,DDR2 only contain Vref pin,DDR3 has Vrefca and Vrefdq which are used as command/address and data reference. DDR3 add a RESET# pin for asynchronous reset DDR3 add a ZQ PIN for internal ZQ calibration reference. ZQ Calibration command is u

2、sed to calibrate DRAM Ron & ODT values. For more detail, refer to Page 107 of DDR3 Standard(JESD79-3E).,DDR2/DDR3 比較之layout,DDR3 layout analyze,DDR3 之Write leveling,DDR3 之Write leveling 實(shí)現(xiàn)方式,DDR3 測試之讀寫分離,DDR3寫操作時(shí)，DQS write preamble 在一個(gè)clk周期內(nèi)先高后低，如下圖所示：,DDR3 測試之讀寫分離(續(xù)),DDR3讀操作時(shí)，DQS read preamble為一個(gè)cl

3、k周期的低電平，如下圖所示：,DDR2/DDR3 比較之CWL,CWL：CAS write latency, its only defined in DDR3. In DDR2, WL = RL-1.,DDR 參數(shù)之CL,CL：CAS Latency 1. CAS latency is the delay, in clock cycles, between the internal Read command and availability of the first bit of output data. 2. programmable CAS Latency 5,6,7,8,9,10,11,

4、12,13 3. CL is only decided by DRAM . Ps, BL: Burst length,DDR 參數(shù)之tRCD,tRCD: RAS to CAS delay time(activate to read/write interval of SDRAM.) tRCD is only decided by DRAM.,DDR 參數(shù)之tRP,tRP: row precharge time 1.When need to read or write other row, the precharge command is used. tRP is the time that p

5、recharge to row. 2. tRP is only decided by DRAM.,DDR3 簡單debug（以P2010為例）,tDSS,tDQSS,tDSH 時(shí)序不滿足時(shí) tDSS,tDQSS,tDSH定義如下：,tDSS,tDQSS,tDSH 時(shí)序不滿足(續(xù)),下圖為未使用WRLVL_EN功能波形，tDSS不滿足要求,tDSS,tDQSS,tDSH 時(shí)序不滿足(續(xù)),使用DDR3 WRLVL_EN后tDSS滿足要求，波形如下：,DQ讀寫波形有較大overshoot,如下圖，當(dāng)寫時(shí)DQS，DQ上存在較大的振鈴。 此時(shí)DRAM端ODT設(shè)置為120ohm.,DQ寫波形有較大overshoot(續(xù)),將DRAM測ODT修改為60ohm后測