1、AgendaDAY 2 567895- 1Synopsys 10-I-011-SSG-013 2007 Synopsys, Inc. All Rights ReservedMore Constraint ConsiderationsTiming AnalysisCompile CommandsEnvironmental AttributesPartitioning for SynthesisUnit ObjectivesAfter completing this unit, you should be able to:n List two effects of partitioning a c

2、ircuit through combinational logicn State the main guideline for partitioning for synthesisn State how partitions are created in HDL coden List two DC commands for modifying partitions5- 2Commands Covered in this Unit5- 3# Automatic ungrouping by DCcompile_ultra # Auto-ungrouping enabled by default

3、compile auto_ungroup area | delaycompile ungroup_all set_dont_touch# Manual re-partioning by the usergroup design NEW_DES cell U23 U2 U3ungroup start_level 2 U23What Is Partitioning? Why Partition?n Partitioning is driven by many needs: Separate distinct functions Achieve workable size and complexit

4、y Manage project in team environment Design Reuse Meet physical constraints, and more 5- 4Partitioning: Dividing large designs into smaller partsPoor Partitioningn Design Compiler must preserve block pin definitions Logic optimization e.g. merging of combinational logic - does not occur across block

5、 boundariesn Path from REG A to REG C may be larger and slower than necessary Poorly partitioned!5- 5How does this partitioning affect synthesis?TOPABCCOMBOCOMBOCOMBOLOGICLOGICLOGIC ABCREGCCLKREGACLKBetter Partitioningn Related combinational logic is grouped into one block: No hierarchy separates co

6、mbinational functions A, B, and Cn Combinational optimization techniques can now be fully exploited Faster and smaller combo logic!n However, no sequential optimization possible at REG C5- 6TOPACCOMBO LOGICREGA & B & CCCLKREG ACLKGuideline: Do not slice through combinational pathsBest Partitioningn

7、Sequential optimization may now integrate some of the combinational logic into a more complex Flip-Flop(JK, Toggle, Muxed Flip-Flops )A SELCLK01DFF_ENBLDFFASEL CLK5- 7TOPACREGCOMBO LOGICAA & B & CCLKREGCCLKGuideline: Do not slice at register inputs rather at outputsCorollary Guideline: Avoid Glue Lo

8、gicTOPACCOMBO LOGIC ACOMBOREG AREG CLOGICCCLKCLKBCOMBOREG BLOGICBCLKPoor Partitioning5- 8Issues:n No combinational optimization between glue logic and combo logic Cn If the top-level blocks A, B and C are large and will be synthesized separately (middle-up compile strategy), an additional compile is

9、 needed at top-levelRemove Glue Logic Between BlocksTOPACCOMBO LOGIC ACOMBO LOGIC C+ GLUEREG AREG CCLKCLKBCOMBOREG BNothing but netsat top-levelLOGICBCLKGood Partitioning5- 9n The glue logic can now be optimized with other logicn Top-level design is only a structural netlist, it does not need to be

10、compiledIn Summary Block 2Block 1Block 3BestPartitioning5- 10n Allows efficient combinational and sequential optimization along timing pathsn Simplifies timing constraints for sub-block synthesis: The arrival times of the inputs to each block is a register ClkQ delay Input logic path delay has almos

11、t the entire clock periodIf partitioning is necessary, try to place the hierarchy boundaries at register outputsREGCCLKREGB2CLKREG B1CLKREGACLKAdditional Guidelinesn Design Compiler has no inherent design size limitn Compile as large a design as possible for best QoR Size is limited only by availabl

12、e memory resources and run timen Separate the synthesizable logic from the non- synthesizable logic apply dont_touch for top- down compile5- 11TOPMIDASYNCHJTAGSYNTHESIZABLE LOGICCLOCK GENPartitioning Within the HDL DescriptionADR_BLKU1DECADR CLKINSTU2OKOKASn entity and module statements define hiera

13、rchical blocks: Instantiation of an entity or module creates a new level of hierarchyn Inference of Arithmetic Circuits (+, -, *, .) can create a new level of hierarchyn Process and Always statements do not create hierarchy5- 12module ADR_BLK (. DEC U1(ADR,CLK,INST); OKU2(ADR,CLK,AS,OK);endmoduleent

14、ity ADR_BLK is. end; architecture STR of ADR_BLK isU1:DEC port map(ADR, CLK, INST); U2:OKport map(ADR,CLK,AS,OK);end STR;Partitioning in Design Compilern Ideally, your RTL-level design follows the “good partitioning” guidelines if so, you are done!n What if your RTL design is poorly partitioned? If

15、possible, re-partition in RTL (recommended)1 Otherwise, re-partition using Design Compilern Partitions can be manipulated in two ways: Automaticu Synthesis re-partitions during compile Manualu User re-partitions prior to compile5- 13Automatic Partitioningn During synthesis, auto-ungrouping can autom

16、aticallymake “smart” re-partitioning choices1: Auto-ungrouping controlled through variables (Unit 11) To report designs auto-ungrouped during synthesis usereport_auto_ungroupn Or, ungroup the entire hierarchy25- 14What if you dont have Ultra and you cant ungroup_all?compile ungroup_allcompile_ultra;

17、 # auto-ungrouping enabled# by defaultcompile -auto_ungroup area|delayManual Partitioninggroupungroup5- 15The group and ungroup commands modify the partitions in a design.Answer: Manually partition prior to compileThe group Command5- 16U1U23TOP_DESIGNDES_AU2U3NEW_DESDES_CDES_Bgroup -design_name NEW_

18、DES -cell_name U23 U2 U3U1U2U3TOP_DESIGNDES_CDES_BDES_Agroup creates a new hierarchical blockThe ungroup Command5- 17What happens if youungroup U23?U1U23TOP_DESIGNNEW_DESDES_Aungroup start_level 2 U23U1U23TOP_DESIGNDES_AU2U3NEW_DESDES_CDES_Bungroup removes either one or all levels of hierarchyExerci

19、se: Poor PartitioningRISC_COREI_PRGRM_CNTI_CONTROLI_ALU180 k gates300 k gatesGlueI_DATA_PATH50 k870 k gatesdata_bus32400 k gates5- 18How would you improve the partitioning of this design for synthesis?Whats wrong with this designs partitioning?Exercise: Move Glue Logic into Sub-blockRISC_COREI_PRGRM

20、_CNTI_CONTROLI_ALU_NEW180 k gates300 k gatesGlue870k gatesI_DATA_PATH50 kdata_bus32400 k gates5- 19What are the advantages of this?current_designset GLUE_CELLS group ungroup Exercise: Combine Other Sub-blocksRISC_COREI_COMBINEDI_PRGRM_CNTI_CONTROLI_ALU_NEW300 k gatesGlueI_DATA_PATH50 k180 k gatesdat

21、a_bus870 k gates920 k gates32400 k gates880 k gates5- 20What are the advantages of this?.group Exercise: Ungroup 2nd Level BlocksRISC_COREI_COMBINEDI_ALU_NEW300 k gatesGlue50 k180 k gatesdata_bus870 k gates920 k gates32400 k gates880 k gates5- 21Whats the advantage of this?.ungroup Partitioning Stra

22、tegies for Synthesisn Do not separate combinational logic across hierarchical boundariesn Place hierarchy boundaries at register outputsn Avoid glue logic at the top leveln Separate non-synthesizable and synthesizable logic5- 22Partitioning for Synthesis: Summaryn Better results - smaller and faster designsn Easier synthesis process - simplified constraints and scriptsn Faster compiles - quicker turnaround5- 23What