1、課程名稱Course集成電路設(shè)計技術(shù)項目名稱Item二輸入與非門、或非門版圖設(shè)計與非門電路的版圖：.spc文件（瞬時分析）：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:03.include H:ml2

2、_125.mdVPower VDD GND 5va A GND PULSE (0 5 0 5n 5n 100n 200n)vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B) v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Res

3、istance.* * * * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6.5)* 4 = F (42.5,6.5)* 6 = GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u * M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5) M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u * M2 DRAIN

4、 GATE SOURCE BULK (39.5 14.5 41.5 23.5) M3 F B 5 GND NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u * M3 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5) M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u * M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5) * Total Nodes: 6* Total Elements: 4* E

5、xtract Elapsed Time: 0 seconds.END與非門電路仿真波形圖（瞬時分析）：.spc文件（直流分析）：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:03.include H:m

6、l2_125.mdVPower VDD GND 5va A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * * * * NODE NAME ALIASES* 1 = VDD (34,37

7、)* 2 = A (29.5,6.5)* 3 = B (55.5,6.5)* 4 = F (42.5,6.5)* 6 = GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u * M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5) M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u * M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5) M3 F B 5 GN

8、D NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u * M3 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5) M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u * M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5) * Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END與非門電路仿真波形圖（直流分析）：

9、或非門電路的版圖：.spc文件（瞬時分析）：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va A GND PUL

10、SE (0 5 0 5n 5n 100n 200n)vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B) v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * * * * NODE NAME ALIASES

11、* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6)* 4 = F (42.5,6.5)* 5 = GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u * M1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5) M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u * M2 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 2

12、3.5) M3 F A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=104.5p PS=60u * M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5) M4 GND B F GND NMOS L=2u W=9.5u AD=104.5p PD=60u AS=57p PS=31u * M4 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5) * Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.EN

13、D或非門電路仿真波形圖（瞬時分析）：.spc文件（直流分析）：* Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va

14、A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* * * * * * * WARNING: Layers with Unassigned FRINGE Capacitance.* * * * * * * * * WARNING: Layers with Zero Resistance.* * * * * NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (

15、55.5,6)* 4 = F (42.5,6.5)* 5 = GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u * M1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5) M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u * M2 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5) M3 F A GND GND NMOS L=2u W=9.5u AD=57p

16、PD=31u AS=104.5p PS=60u * M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5) M4 GND B F GND NMOS L=2u W=9.5u AD=104.5p PD=60u AS=57p PS=31u * M4 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5) * Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END或非門電路仿真波形圖（直流分析）：課程名稱Course集成電路設(shè)計技術(shù)項目名稱Item

17、二輸入與非門、或非門版圖設(shè)計目的Objective1. 掌握利用E-EDIT進行IC設(shè)計方法，設(shè)計二輸入與非門版圖并仿真2. 掌握利用L-EDIT進行IC設(shè)計方法，設(shè)計二輸入或非門版圖并仿真3. 領(lǐng)會并掌握版圖設(shè)計最優(yōu)化實現(xiàn)方法。內(nèi)容（方法、步驟、要求或考核標準及所需工具、設(shè)備等）一、 實訓設(shè)備與工具1 PVI計算機一臺；2 Tanner Pro集成電路設(shè)計軟件二、 實訓方法、步驟與要求1 二輸入與非門電路的線路結(jié)構(gòu) 2 二輸入或非門電路的線路結(jié)構(gòu)3 CMOS倒相器電路的版圖4 根據(jù)與非門、或非門線路結(jié)構(gòu)，在一個工程中，重新新建兩個新CELL，分別對應(yīng)與非門和或非門版圖，并設(shè)計與非門、或非版圖

18、結(jié)構(gòu)。1） 按照最佳噪聲容限合理設(shè)計與非門、或非門單元電路中的N管和P管的尺寸；2） 版圖結(jié)構(gòu)最簡單，版圖尺寸最?。唬ǜ叨染鶠?0um）3） 加入正確的電路端口，并在抽取的網(wǎng)表中存在A、B和F；4） 版圖設(shè)計規(guī)則檢查（DRC）無錯誤5 熟記基本、重要的版圖設(shè)計規(guī)則6 進行CMOS與非門、或非門版圖網(wǎng)表抽取，加入仿真命令，進行瞬時和直流分析 Tool Extract General選項 Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext Spice Extract Output File: d:designnand2.spc Output選項 Comment: Write Node name Names Write Verbose Spice Statement Spice Include Statement . Include c:ta