1、Chapter 3 Digital Circuit（數字電路）The electrical aspects of digital circuits（數字電路中的電氣知識）1Basic logic functionOR gate0 0 00 1 01 0 01 1 1Truth table （真值表）A B ZZ = A BAND gateNOT gateZ = A + BZ = A0 0 00 1 11 0 11 1 1Truth table （真值表）A B ZA Z0 11 0Truth table （真值表）ABZABZAZ2NAND and NORNAND gate logic exp

2、ression： Z = ( A B ) logic symbol：NOR gate logic expression： Z = ( A + B ) logic symbol：&133.1 Logic Signals and Gates（邏輯信號和門電路）在電路中如何表示0和1？ 高電平（HIGH）和低電平（LOW）高電平對應 0 還是 1？正邏輯positive10負邏輯negative104如何在輸入控制下獲得高、低電平？VOUTVINVccR獲得高、低電平的基本原理當S閉合，Vout=當S斷開，Vout=0 VVcc(LOW)(HIGH)對開關的要求？可以做開關的器件S53.2 Logi

3、c Family （邏輯系列）TTL（Transistor Transistor Logic） CMOS（Complementary MOS） ECL（Emitter- Coupled Logic）Chips from the same family have similar input, output, and internal circuit characteristics, but perform different logic function.（同一系列的芯片具有類似的輸入、輸出及內部電氣特性，但邏輯功能不同。）Chips from the same family can be in

4、terconnected to perform any desired logic function.Chips from the different families may not be compatible.（不同系列的芯片可能不匹配）63.3 CMOS Logic CMOS logic levelsLogic 1（HIGH）Logic 0（LOW）5.0V3.5V1.5V0.0VundefinedTypical：5V power supplyOther power supply：3.3V or 2.7V71、MOS TransistorsN-channel and P-channel

5、Normally Vgs = 0 Vgs = 0 Rds is very high（106） 截止狀態(tài)（off） Vgs Rds 導通狀態(tài)（on）漏極 drain源極 source柵極 gateVgs+N channel源極 source漏極 drain柵極 gate+VgsP channel8Normally：Vgs 兆歐）無論柵電壓如何 柵漏、柵源之間幾乎沒有電流 （漏電流 leakage current , A）柵極與源和漏極之間有電容耦合 信號轉換時，電容充放電，功耗較大1、MOS Transistors10MOS管的基本開關電路vOvIVccR只要電路參數選擇合理輸入低，截止，輸出高

6、輸入高，導通，輸出低vI+vO+iD+ VDDRDDGS112、Basic CMOS Inverter Circuit工作原理1、VIN = 0.0VVGSN = 0.0V，Tn offVGSP = VIN VDD = 5.0V，Tp onVOUT VDD = 5.0V2、VIN = VDD = 5.0VVGSN = 5.0V，Tn onVGSP = VIN VDD = 0.0V ，Tp offVOUT 0VDD = +5.0VVOUTVINTpTnGDSSVinVoutLOWHIGHHIGHLOW122、 Basic CMOS Inverter CircuitVDD = +5.0VVOUTV

7、INTpTnVinVoutLOWHIGHHIGHLOW一個輸入端，實現對兩個開關的控制 PMOS開關接1（正電源）NMOS開關接0（接地） 為確保輸出具有確定的1或0，開關必須一通一斷，不能全通或全斷133、CMOS NAND Gate 工作原理：1、either input is LOW T1、T3至少有一個截止， T2、T4至少有一個導通；Z為高（ VDD）2、both inputs are HIGH T1、T3都導通， T2，T4都截止， Z為低（ 0V）VDD = +5.0VZABT1T2T4T3思考：兩種開關能否都采用串聯(lián)形式？144、CMOS NOR Gate工作原理： 1、Bot

8、h inputs are LOW T1、T3都截止， T2，T4都導通， Z為高（ VDD） 2、either input is HIGH T1、T3至少有一個導通， T2、T4至少有一個截止； Z為低（ 0V）VDD = +5.0VZABT1T2T4T315VDD = +5.0VZABVDD = +5.0VZABNOR GateNAND Gate小結：每個輸入控制一對互補的晶體管：P接1，N接0； 基本邏輯體現在N網絡上，P網絡采用對偶形式；由于N網絡接地，因此輸出反相（非）； 16VDD = +5.0VABZCD5、CMOS AND-OR-INVERT Gates176、CMOS OR-A

9、ND-INVERT Gates187、 Fanin（扇入）The number of inputs that a gate can have in a particular logic family.The additive “on” resistance of series transistors limits the fan-in of CMOS gates.（導通電阻的可加性限制了CMOS門的扇入數）198、Noninverting Gates（非反相門）VDD = +5.0VAZNoninverting buffer（非反相緩沖器）2-input AND gate203.4 Elect

10、rical Behavior of CMOS Circuits（CMOS電路的電氣特性）物理上的而不是邏輯上的Logic Voltage levels（邏輯電壓電平）DC noise margins（直流噪聲容限）Fanout（扇出）Speed（速度）Power consumption（功耗）Noise（噪聲）Electrostatic discharge（靜電放電）Open-drain outputs（漏極開路輸出）Three-state outputs（三態(tài)輸出）21data sheet（數據表）（P.99）223.5 CMOS Static Electrical Behavior（CMO

11、S穩(wěn)態(tài)電氣特性）VDD = +5.0VVOUTVINTpTnVOUTVIN5.01.53.55.0Transfer characteristic 0 1 0123Logic LevelHIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminVOUTVIN5.01.53.55.0Transfer characteristic24HIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminVCC0.1VGND0.1V0.7VCC0.3VCCLogic Level25DC noise margin（直流噪聲容限）A measure of how much no

12、ise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input. 門電路的抗干擾能力HIGHABNORMALLOWVOLmaxVILmaxVIHminVOHminHIGH-state DC noise margin：VNH=VOHmin1- VIHmin2LOW-state DC noise margin： VNL=VILmax2- VOLmax1Gate 1Gate 22674HC driving 74HCT HIGH-state:

13、 4.4 2.0 = 2.4V LOW-state: 0.8 0.1 = 0.7V74HCT driving 74HC HIGH-state: 4.4 3.85 = 0.55V LOW-state: 1.35 0.1 = 1.25VCompute the LOW-state and HIGH-state DC noise margins.p.146 Table 3-6 p.147 Table 3-774HC FamilyVOHminC= 4.4VVOLmaxC= 0.1VVIHmin = 3.85VVILmax = 1.35V74HCT FamilyVOHminC= 4.4VVOLmaxC=

14、0.1VVIHmin = 2.0VVILmax = 0.8V27Circuit Behavior with Resistive Loads （帶電阻性負載的電路特性）Require nontrivial amounts of current to operate要求有一定的驅動電流才能工作VCCAZVCCRThevRpRnVThev +VOUTVIN28VOUT 1MRnRThevVThev +VOLmaxIOLmax29VOHminIOHmaxVCC = + 5.0VRpRn1M+If the output is HIGHVOUT = VOHminThe output is said to

15、source current. sourcing current （提供電流）IOHmax：The maximum current that the output can source in the HIGH state while still maintaining an output voltage no less than VOHmin30VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0If the output is HIGH, the sourcing current is：I

16、f the output is LOW, the sinking current is：31Determine whether the output drive specifications of the 74LS00 over the commercial operating range are exceeded.from Table 3-4，VOHMIN=3.84V VOLMAX=0.33V IOHMAX=-4mA IOLMAX= 4mAIn the HIGH state, the gate must pull the output up to 3.84V, requiring Io=3.

17、84/1000-(5-3.84)/1000=2.68mA，is not out of spec.In the LOW state, the output pulls down to 0.33V (the maximum spec). Then the output current is Io=(5-0.33)/1000-0.33/1000=4.34mA, out of spec.VCC = + 5.0VR1=1000R2=1000VOUT32Circuit Behavior with Nonideal Inputs(非理想輸入時的電路特性)VCC = + 5.0V4002.5kVIN 1.5V

18、VOUT 4.31VVCC = + 5.0V4k200VIN 3.5VVOUT 0.24V輸出電壓變壞（有電阻性負載時更差）更糟糕的是：輸出端電流 ，功耗 33扇出（fan-out）The number of inputs that the gate can drive without exceeding its worst-case loading specifications. (在不超出其最壞情況負載規(guī)格的條件下，一個邏輯門能驅動的輸入端個數。)Fanout must be examined for both possible output states, HIGH and LOW. o

19、verall fanoutmin（HIGH-state fanout，LOW-state fanout）DC fanoutAC fanout3474AHC driving 74HC LOW-State fanout：Compute the maximum fanout HIGH-State fanout：CMOS: 74AHCIOHmaxC = 50 AIOLmaxC = 50 A IIHmax = 1 A IILmax = 1 ACMOS: 74HCIOHmaxc = 20 AIOLmaxc = 20 A IIHmax = 1 A IILmax = 1 AOverall fanout：Min

20、 (HIGH-state fanout, LOW-state fanout)=50Table 3-6、3-735Effects of Loading (負載效應) 當輸出負載大于它的扇出能力時輸出電壓變差（不符合邏輯電平的規(guī)格）傳輸延遲和轉換時間變長溫度可能升高，可靠性降低，器件失效36Unused Inputs (不用的CMOS輸入端)Unused CMOS inputs should never be left unconnected (or floating).XZ1k+5VXZXZ增加了驅動信號的電容負載，使操作變慢373.6 CMOS Dynamic Electrical Behav

21、ior ( CMOS動態(tài)電氣特性 ) Both the speed and the power consumption of the CMOS device depend to a large on “AC” or dynamic characteristics of the device and its load.Speed depends on two characteristics：transition time（轉換時間）propagation delay（傳播延遲）The amount of time that the output of a logic circuit takes

22、to change from one state to another .The amount of time that is takes for a change in the input signal to produce a change in the output signal.38Transition Time (轉換時間) rise time (tr ) and fall time (tf )Fig 3-36 P.11539Transition Time (轉換時間) rise time (tr ) and fall time (tf )VCC = + 5.0VRLRpRnVL+C

23、L電容兩端電壓不能突變在實際電路中可用時間常數近似轉換時間The “on” resistances of the transistors （晶體管的“導通”電阻）stray capacitance（寄生電容）40Propagation delay（傳播延遲）P.121 圖3-42VINVOUTSignal path: the electrical path from a particular input signal to a particular output signal of a logic element. 41Power Consumption（功率損耗）動態(tài)功耗的來源：兩個管子瞬間

24、同時導通產生的功耗 PT對負載電容充、放電所產生的功耗 PLVDD = +5.0VVOUTVINTpTnStatic Power consumption and dynamic power dissipationCL42Power Consumption（功率損耗）動態(tài)功耗的來源：兩個管子瞬間同時導通產生的功耗 PT對負載電容充、放電所產生的功耗 PLStatic Power consumption and dynamic power dissipationVCC 的大小輸入波形的好壞輸入信號頻率負載電容輸入信號頻率 (VCC ) 2 433.7 Other CMOS Input and Ou

25、tput Structures （其他CMOS輸入輸出結構）Transmission Gates 傳輸門When EN = 0，EN_L = 1， transistor “off ”， A and B are disconnected.When EN = 1，EN_L = 0， transistor “on ”， a low-impedance connection.雙向器件傳播延遲非常短可以傳送模擬信號 ENEN_LAB44Schmitt-Trigger Input（施密特觸發(fā)器輸入）VOUTVIN5.02.12.95.0Transfer characteristicVT+VT-inputt

26、hresholdVT+VT-采用內部反饋，邊沿更陡Hysteresis（滯后）：the difference between the two thresholds. Logic symbol：45波形變換Schmitt-Trigger Input（施密特觸發(fā)器輸入）46Device operation with slowly changing inputsSchmitt-Trigger Input（施密特觸發(fā)器輸入）47脈沖整形Schmitt-Trigger Input（施密特觸發(fā)器輸入）48Three-State Outputs （三態(tài)輸出）VCCOUTENAIf EN=0， C=1, Tp

27、 off B=1, D=0, Tn off high-impedance, Hi-Z（or floating state）If EN=1， C=A , B=0 , D=A OUT=ABCDTpTnAENOUT邏輯符號49輸出電平？造成邏輯混亂很大的負載電流同時流過輸出級可使門電路損壞VCCAZ有源上拉active pull-upVCCB低高有源上拉的CMOS器件其輸出端不能直接相聯(lián)1001M1001M50特點：只能輸出L態(tài)和Z態(tài)；可以外接上拉電阻實現H態(tài)；多個器件輸出端可以直接連接，“線與邏輯”；Open-Drain Outputs（漏極開路輸出）51Open-Drain Outputs（漏極

28、開路輸出）ABZVCCVCCR pull-up resistorABZ邏輯符號希望盡量小，減少上升時間但若太小則吸收電流太大應用：驅動LED、線與、 驅動多源總線上拉電阻的計算：最大值：提供后級所需最大高電平輸入電流時，能夠保障輸入高電平電壓；最小值：輸出低電平時，能夠保障不超過最大輸出電流；外接上拉電阻會顯著降低器件轉換速度； 5253ABZVCCVCCRCDVCCZ = Z1 Z2 = (AB) (CD) Z1Z2線與Open-Drain Outputs（漏極開路輸出）533.10 Bipolar logicDiode 門限電壓反向擊穿漏電流viVTI s+RfVd正偏（導通）+反偏（截止

29、）54Diode logicABD1D2RVCCY 級聯(lián)時會出現電平偏移 不能直接驅動負載 通常用于集成電路內部的邏輯單元02V LOW logic 023V undefined35V HIGH logic 1二極管與門3.10 Bipolar logic55Bipolar Junction transistor (雙極結型晶體管)截止區(qū)放大區(qū)飽和區(qū)基極basecollector集電極發(fā)射極emitterVCCvo+-vi+-RBRCiCTransistor inverter56Schottky-clamped tansistor（肖特基晶體管）三極管內部電荷的建立和消散都需要時間 存儲時間（

30、傳輸延遲的重要部分）確保晶體管正常工作時不進入深度飽和利用肖特基二極管基極集電極發(fā)射極573.10.3 Transistor-Transistor Logic (晶體管晶體管邏輯) TTL系列 低態(tài)：0.00.8V 高態(tài)：2.05.0V58Logic Families （邏輯系列）3.8 CMOS Logic FamiliesHC、HCT 高速AHC、AHCTFCT、FCT-T3.10.6 TTL familiesH高速S肖特基L低功耗（LS）A高級（AS、ALS）F快速7454FAM nn器件標號功能對稱輸出驅動59CMOS/TTL接口需要考慮：噪聲容限、扇出、電容負載1、DC noise margingate1gate 2被驅動門驅動門低態(tài)噪聲容限VNL=VILmax2- VOLmax1高態(tài)噪聲容限VNH=VOHmin1- VIHmin26074HC driving 74LS HIGH state: 3.84 2.0 = 1.84V LOW state: 0.8 0.33 = 0.47V74LS driving 74HC HIGH state: 2.7 3.85 =-1.15V LOW state: 1.35 0.5 = 0.85V1、DC Noise Margi