ForStudentsChapter8-Counters(PartV)Digital

Electronics-Lecture

16各觸發(fā)器的輸入：驅(qū)動(dòng)各觸發(fā)器的輸出：狀態(tài)YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB時(shí)序邏輯電路設(shè)計(jì)：為使觸發(fā)器的輸出狀態(tài)按給定要求變化，輸入應(yīng)滿足什么條件？8-4

Design

of

Synchronous

Counters（同步計(jì)數(shù)器的設(shè)計(jì)）關(guān)鍵：得到觸發(fā)器各輸入端的驅(qū)動(dòng)方程，該輸入可使觸發(fā)器狀態(tài)按既定要求變化！3YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBSTEP

1: Create

aState

DiagramSTEP

2: Derive

a

Next-State

Table4YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBExample:

Design

a

3-bit

Gray

code

counter

P326STEP

3:

Flip-FlopTransition

TableJ

Kn+100000011100110110100011011011

1

1

0狀態(tài)轉(zhuǎn)換表5YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBSTEP

4:

Karnaugh

Maps根據(jù)狀態(tài)轉(zhuǎn)換過(guò)程得出描述每個(gè)觸發(fā)器輸入端邏輯關(guān)系的圖YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBSTEP

5:

Logic

Expressions

for

Flip-Flop

InputsYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBSTEP

6: Counter

ImplementationJ0

Q2

Q1K0

Q2

Q1J2

Q1Q0K2

Q1Q0J1

Q2Q0K1

Q2Q0YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBA

general

design

procedure

for

synchronous

counter11YJ,Departmentof Electrical&ElectronicTechnology,SAEE,USTBP329Specify

the

counter

sequence:draw

the

state

diagram

and

next-state

table明確時(shí)序（狀態(tài)轉(zhuǎn)換）關(guān)系Develop

a

transition

table

showing

the

FF’s

inputsrequired

for

each

transition.確定觸發(fā)器類(lèi)型及觸發(fā)器輸入和輸出狀態(tài)轉(zhuǎn)移關(guān)系Draw

Karnaugh

maps

for

each

FF’s

inputs根據(jù)狀態(tài)轉(zhuǎn)換過(guò)程得出每個(gè)觸發(fā)器輸入端邏輯關(guān)系的

圖Derive

the

Excitation

equation

for

each

FF’s

inputs根據(jù)要求的輸出狀態(tài)變化確定觸發(fā)器的驅(qū)動(dòng)方程Implement

the

circuit實(shí)現(xiàn)電路P330:

Example

8-5Design

a

counter

with

the

irregular

binary

countsequence

shown

in

the

state

diagram.

Use

J-Kflip-flops.Step

1: Create

aState

DiagramYJ,Departmentof Electrical&ElectronicTechnology,SAEE,USTBStep

2:

Next-state

tableStep

3:

Transition

tablefor

a

J-K

flip-flop13YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

4

and

5: Kmap

and

logicexpressions

for

flip-flops

inputsYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

4

and

5: Kmap

and

logicexpressions

for

flip-flops

inputsYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

4

and

5: Kmap

and

logicexpressions

for

flip-flops

inputsYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

6:

ImplementationJ2

Q1,

K2

Q1;

J1

1,

K1

1;

J0

1,

K0

Q217YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBP332: Example

8-6Develop

asynchronous

3-bitup/down

counter

witha

Gray

codesequence.

Thecounter

should

countup

when

anUP/DOWN

controlinputs

is

1

and

countdown

when

thecontrol

input

is

0.Moore

Type

or

Mealy

Type?YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

2:

Next-state

tableThe

control

input

Y,

istreated

as

a

fourth

variable19YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

4

and

5:YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBStep

6:

The

circuitYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB補(bǔ)例：設(shè)計(jì)一個(gè)串行數(shù)據(jù)檢測(cè)器。對(duì)它的要求是：連續(xù)輸入3個(gè)或3個(gè)以上的1時(shí)輸出為1，其他輸入情況下輸出為0。步驟一：邏輯抽象并畫(huà)出狀態(tài)轉(zhuǎn)換圖確定輸入變量：輸入數(shù)據(jù)，用X表示。確定輸出變量：檢測(cè)結(jié)果，用Y表示。對(duì)狀態(tài)

：沒(méi)有輸入1以前的狀態(tài)為S0，輸入一個(gè)1以后的狀態(tài)為S1，連續(xù)輸入兩個(gè)1以后的狀態(tài)為S2，連續(xù)輸入3個(gè)或3個(gè)以上1以后的狀態(tài)為S3。YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB4)根據(jù)題意畫(huà)出原始的狀態(tài)轉(zhuǎn)換表XSnSn

1/

Y01S0S0/0S1/0S1S0/0S2/0S2S0/0S3/1S3S0/0S3/1沒(méi)有輸入1以前的狀態(tài)為S0輸入一個(gè)1以后的狀態(tài)為S

1連續(xù)輸入兩個(gè)1以后的狀態(tài)為S2連續(xù)輸入3個(gè)或3個(gè)以上1以后的狀態(tài)為S324YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB5)狀態(tài)化簡(jiǎn)S

nXSn

1

/

Y01S0S1S2S3S0/0S0/0S0/0S0/0S1/0S2/0S3/1S3/1等價(jià)狀態(tài)

——相同的輸入下轉(zhuǎn)換到同樣的次態(tài)，并有相同的輸出。等價(jià)狀態(tài)S

n

XS

n

1/

Y01S0S0/0S1/0S1S0/0S2/0S2S0/0S2/1簡(jiǎn)化25YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB2N

1

M

2N其中，M是總狀態(tài)數(shù)，N是需用觸發(fā)器個(gè)數(shù)；此例M=3，N=2按一定的規(guī)律對(duì)化簡(jiǎn)后的每一個(gè)狀態(tài)都選定一個(gè)N位二進(jìn)制代碼來(lái)表示。本例取觸發(fā)器狀態(tài)Q1Q0的00、01和10分別代表S0、S1、S2S

n

XS

n

1/

Y01S0S0/0S1/0S1S0/0S2/0S2S0/0S2/1presentstateNew

stateX=0X=1Q1Q0Q1Q0/YQ1Q0/Y0000/001/00100/010/01000/010/111XX/XXX/X6)狀態(tài)分配（狀態(tài)編碼）確定所使用觸發(fā)器的個(gè)數(shù)：26YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB0101Qn

Qn1

000

11

1000/000/0xx/x00/001/010/0xx/x10/11)將此

圖分解為Q1、Q0和Y的3個(gè)

圖。01XQnQn1

000

0111

1000x001x11Qn101XQnQn1

000

01

11

1000x010x00Qn101XQnQn1

00011

100100x000x1Y步驟二：由狀態(tài)轉(zhuǎn)換表得到觸發(fā)器驅(qū)動(dòng)方程補(bǔ)充：根據(jù)狀態(tài)方程用比對(duì)法直接得出驅(qū)動(dòng)方程。YQn1Qn

11

0狀X態(tài)轉(zhuǎn)換表YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB011

10XQnQn1

0000100x001x11Qn10011110X1QnQn1

00000x010x00Qn10111

10X1QnQn1

0000100x000x1Y2)化簡(jiǎn)3個(gè)圖，得到狀態(tài)方程和輸出方程。0Qn1

XQ

XQ1

1Qn1

X01

0Y

XQ1YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBQn

1

XQ

XQ

XQ

XQ

(Q

Q

)1

0

1

0

1

11

(XQ

0

)Q

1

XQ

13)比照選定觸發(fā)器的特性方程，變換狀態(tài)方程的形式，以得出驅(qū)動(dòng)方程。00Q

n

10

X

(XQ

)Q

1Q1

0

1則驅(qū)動(dòng)方程為：J1

XQ0J0

XQ1K1

XK0

1本檢測(cè)電路選用JK觸發(fā)器構(gòu)成：Qn1

JQn

KQn變換：YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB步驟三：根據(jù)驅(qū)動(dòng)方程、輸出方程畫(huà)出邏輯圖。J1

XQ0K1

XJ0

XQ1YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB0K

11Y

XQ步驟四：檢查設(shè)計(jì)的電路能否自啟動(dòng)。00111

10X31YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB1

00000/000/0xx/x00/001/010/0xx/x10/1由前面的例題可知，次態(tài)為任意項(xiàng)的狀態(tài)是無(wú)效狀態(tài)。Qn

Qn如左圖中的11狀態(tài)為無(wú)效狀態(tài)。1若使全部無(wú)效狀態(tài)的次態(tài)為有效狀態(tài)，則此電路必能自啟動(dòng)。1X1

000

01

11

1000x001x11Qn1

010111

10XQnQn

QnQn1

00000x010x000Qn1圖化簡(jiǎn)中，任意項(xiàng)被包括在

圈中相當(dāng)于取值為1，反之為0。即化簡(jiǎn)時(shí)已為無(wú)效狀態(tài)指定了次態(tài)。Q1Q0=11的次態(tài)：X=0時(shí)為00，X=0時(shí)為10。只需要檢查所指定次態(tài)是否屬于有效循環(huán)，便知該電路是否能夠自啟動(dòng)。時(shí)序邏輯電路設(shè)計(jì)過(guò)程中，有意指定無(wú)效狀態(tài)的次態(tài)為有效狀態(tài)，即可直接設(shè)計(jì)出能夠自啟動(dòng)的電路。YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB同步邏輯電路的設(shè)計(jì)步驟YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBAssignmentP357：19----同步計(jì)數(shù)器設(shè)計(jì)34YJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTB8-7

Counter

Applications（計(jì)數(shù)器應(yīng)用）Digital

clockYJ,DepartmentofElectrical&ElectronicTechnology,SAEE,USTBLogic

diagram

of

typical

divide-by-60

counter.(the

right-most

bit

is

the

LSB)P299

74F162:

Synchronous

BCD

decade

coun